Flash Memory Parity Buffering for Higher RAIN Write Rate
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Solution Overview
Problem
Conventional Redundant Array of Independent Nodes (RAIN) techniques for memory storage devices result in insufficient valid physical erasing units due to increased parity code storage requirements, reducing the storage capacity and write rate.
Innovation Solution
A memory management method that involves temporarily storing parity codes in a buffer memory and performing encoding operations to reduce parity code storage capacity and increase the range of cache program operations in super physical erasing units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional RAIN technique is used to maintain data integrity, then data reliability is improved, but the number of valid physical erasing units decreases due to increased parity code storage requirements
Solution Approach 1:
The patent divides the super physical erasing unit into multiple physical erasing units across different memory planes, and further segments the parity code generation into multiple stages. By segmenting the 16 physical erasing units into 4 planes with 4 units each, and generating parity codes in batches, the system reduces the immediate storage burden while maintaining RAIN protection across all units.
Solution Approach 2:
The patent performs preliminary generation of parity codes for the first N physical erasing units before completing data writing to all M units. These preliminary parity codes are stored in buffer memory, allowing subsequent parity codes to be generated using encoding operations on the preliminary codes, thereby reducing the total capacity needed for parity storage.
2Reliability
If parity code ratio is increased to protect more physical erasing units, then data reliability is improved, but write rate decreases due to reduced valid blocks
Solution Approach 1:
The system performs preliminary generation and buffering of parity codes for the first N physical erasing units before completing data writing to all M units. This preliminary action allows parallel processing of data writing and parity generation, reducing the critical path delay and improving write throughput while maintaining high parity code protection ratios.
Solution Approach 2:
The patent implements continuous parity code generation through encoding operations. After generating initial parity codes for N units, the system continuously generates remaining parity codes by encoding operations on the buffered codes and incoming data, ensuring uninterrupted write operations and maintaining high write rates even with increased parity requirements.
3Reliability
If more capacity is allocated for parity code storage, then data integrity is improved, but storage capacity for user data decreases
Solution Approach 1:
The patent segments the parity code storage across multiple physical erasing units and memory planes rather than dedicating a single large portion to parity codes. By distributing parity storage across 4 planes with coordinated parity generation, the system optimizes the balance between protection capacity and user data capacity within the same physical space.
Solution Approach 2:
The system dynamically adjusts the number of physical erasing units N for which preliminary parity codes are generated and buffered, based on available buffer capacity and write workload characteristics. This parameter adjustment allows optimization of the trade-off between parity storage overhead and user data capacity utilization.
4Productivity
If buffer memory is used for temporary parity code storage, then write rate is improved through parallel processing, but device complexity increases
Solution Approach 1:
The patent divides the buffer memory into multiple buffers corresponding to different planes or parity code groups, allowing independent management and processing of parity codes for each segment. This segmentation simplifies the control logic compared to managing a single large buffer, as each buffer can be handled independently with standardized procedures.
Data Source
AI summary
A memory management method, a memory storage device, and a memory control circuit unit are disclosed. The memory management method includes: writing first data into N super physical programming units of a first super physical erasing unit in a plurality of super physical erasing units; generating N first temporary parity codes according to the first data and storing the N first temporary parity codes in a buffer memory; writing second data into M super physical programming units of a second super physical erasing unit in the plurality of super physical erasing units; performing an encoding operation on the second data and the N first temporary parity codes to generate N first parity codes; and writing the N first parity codes into the second super physical erasing unit.