Flash Controller Parity Calculation via Segmented RAID ECC
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Solution Overview
Problem
Flash controllers spend significant time and computational resources calculating parities across data pages of page groups in flash memory devices, leading to inefficiencies in programming and error correction.
Innovation Solution
A method and apparatus that utilize a host interface controller, direct memory access controller, and RAID ECC engine to efficiently calculate and program parities for page groups by optimizing the bus architecture and interface settings, allowing simultaneous data transmission and parity calculation, thereby reducing wait times and resource usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the flash controller calculates parities across data pages of page groups using traditional methods, then error correction capability is ensured, but time and computational resources are significantly consumed
Solution Approach 1:
The patent divides the page group into multiple sub-page groups and calculates parities for each sub-page group separately using parallel processing. This segmentation allows the parity calculation to be distributed across multiple processing units simultaneously, reducing the total calculation time while maintaining the overall error correction capability of the page group
Solution Approach 2:
The patent performs preliminary parity calculations on subsets of pages before combining results. By pre-calculating parities for smaller sub-page groups and then combining them, the system reduces the computational burden of calculating parities across the entire page group at once, thereby reducing time consumption while ensuring accurate error correction
2Reliability
If the flash controller calculates parities across data pages of page groups using traditional methods, then error correction capability is ensured, but computational resources are significantly consumed
Solution Approach 1:
The patent segments the page group into multiple sub-page groups and processes them in parallel. This division reduces the computational load on individual processing units, allowing more efficient use of available computational resources while maintaining the overall error correction capability through combined parity results
Solution Approach 2:
The patent calculates parities for subsets of pages (partial action) rather than requiring all pages to be processed sequentially. By computing parities for multiple sub-page groups simultaneously and combining results, the system achieves the required error correction capability with reduced total computational resource consumption
3Ease of operation
If the host I/F controller stores user data on pages in RAM through bus architecture and outputs to engine for parity calculation, then data processing is enabled, but bus contention increases programming time
Solution Approach 1:
The patent enables continuous data flow by having the host I/F controller store user data in RAM and simultaneously output it to the processing engine without waiting for the engine to finish previous operations. This continuous operation eliminates idle time and reduces bus contention by keeping the data pipeline full, thereby reducing overall programming time while maintaining ease of data processing
Solution Approach 2:
The host I/F controller preliminarily stores user data in RAM before the engine processes it for parity calculation. This preliminary storage action allows the engine to begin processing as soon as data is available, reducing waiting time and bus contention by overlapping data transfer and processing operations
Data Source
AI summary
The invention introduces a method for programming data of page groups into flash units to include steps for: obtaining, by a host interface (I/F) controller, user data of a page group from a host side, wherein the page group comprises multiple pages; storing, by the host I/F controller, the user data on the pages in a random access memory (RAM) through a bus architecture, outputting the user data on the pages to an engine via an I/F, and enabling the engine to calculate a parity of the page group according to the user data on the pages; obtaining, by a direct memory access (DMA) controller, the parity of the page group from the engine and storing the parity of the page group in the RAM through the bus architecture; and obtaining, by a flash I/F controller, the user data on the pages and the parity of the page group from the RAM through the bus architecture, and programming the user data on the pages and the parity of the page group into a flash module.