Flash Memory Parity Code Distribution for Storage Efficiency
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Solution Overview
Problem
Conventional flash memory controllers inefficiently utilize memory space by dedicating one-eighth of a data block for parity check codes, reducing the effective storage capacity and user experience due to high error rates during programming failures, word line opens, or word line shorts.
Innovation Solution
Implementing a RAID-like error correction code encoding operation in a flash memory apparatus, which classifies data into groups, generates parity check codes, and performs internal copy operations to store these codes efficiently across multiple storage blocks, allowing for error correction during programming failures and physical errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flash memory controllers program parity check codes into dedicated pages, then error correction capability is improved, but memory space utilization deteriorates
Solution Approach 1:
The patent merges the functions of data storage and parity check code storage by allowing parity check codes to be programmed into data pages alongside actual data. This combination approach eliminates the need for separate dedicated parity pages, thereby improving memory space utilization while maintaining error correction capability through the integrated RAID-like encoding scheme
Solution Approach 2:
Data pages are designed to serve multiple functions simultaneously: storing both user data and parity check codes. This multi-functionality allows the same memory space to provide both data storage capacity and error correction functionality, resolving the contradiction between reliability and space utilization
2Reliability
If one eighth of memory space is allocated for parity check codes, then error correction capability is improved, but effective storage capacity deteriorates
Solution Approach 1:
Instead of allocating a fixed one-eighth portion of memory for parity check codes, the patent implements a partial action approach where parity check codes are distributed throughout data pages based on actual error correction needs. This selective allocation provides error correction capability only where necessary, maximizing effective storage capacity while maintaining reliability
Solution Approach 2:
The patent changes the parameter of parity check code allocation from a fixed ratio (one-eighth) to a flexible, dynamic distribution scheme. By modifying how parity codes are positioned and allocated within memory pages, the system achieves both error correction capability and maximized effective storage capacity
Data Source
AI summary
A method used in a flash memory module having a plurality of storage blocks is disclosed. Each storage block can be used as a first block or a second block wherein a cell of the first block is arranged for storing data of 1 bit and a cell of the second block is arranged for storing data of at least 2 bits. The method includes: classifying data to be programmed into a plurality of groups of data; executing error code encoding to generate a corresponding parity check code to store the groups of data and the corresponding parity check code to at least one block of first blocks; and after completing storing the groups of data, performing an internal copy operation upon the groups of data and the corresponding parity check code from the at least one block of the first blocks to at least one second block.