Flash Path Circuit Embedding High Voltage Within Low Voltage Paths
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Solution Overview
Problem
Non-volatile memory devices face inefficiencies due to separate high voltage (HV) and low voltage (LV) signal paths, which occupy excessive silicon area and require careful control to maintain safe operating areas for transistors, potentially leading to damage.
Innovation Solution
The implementation of a Common Source Line (CSL) architecture, where HV signals are embedded within LV signal paths, sharing components to reduce silicon area usage and optimize signal propagation, with a word line driver having separate paths for fast LV and slow HV signals to manage operations like read, program, and erase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate high voltage and low voltage signal paths are used, then transistor safe operating areas are maintained, but silicon area usage increases
Solution Approach 1:
The patent merges the high voltage signal path with the low voltage signal path by embedding the HV path within the LV path. Specifically, the HV signal is transmitted through the same source line that carries LV signals, allowing both voltage regimes to share common routing infrastructure and reducing overall silicon area consumption while maintaining transistor safety through controlled voltage application timing
2Reliability
If high voltage signals are transmitted through separate paths, then signal integrity is maintained, but device complexity increases
Solution Approach 1:
The source line is designed to serve multiple functions: it carries both low voltage signals during normal operation and high voltage signals during program/erase operations. The word line driver is also multi-functional, capable of switching between driving LV read signals and HV program/erase signals through the same physical path, thereby reducing the need for dedicated separate routing infrastructure
3Area of stationary object
If high voltage signals are embedded within low voltage signal paths, then silicon area is reduced, but transistor damage risk increases
Solution Approach 1:
Before applying high voltage signals through the embedded path, the patent ensures that the target transistor is properly selected and that other transistors in the path are in non-conductive states. The word line driver switches to HV mode only when the specific memory cell is selected, and appropriate voltage levels are applied in advance to ensure safe operating conditions before the actual program/erase operation begins
Solution Approach 2:
The signal path dynamically switches between LV and HV modes based on the operational requirements. The word line driver can rapidly transition between driving LV read signals and HV program/erase signals, and the circuit automatically adjusts voltage levels and routing based on the current operation type, ensuring that HV signals are only present when and where needed
Data Source
AI summary
A circuit includes a first word line coupled to a non-volatile memory (NVM) cell. A first path includes a first inverter and a transistor. The transistor is coupled to the word line. The first path is coupled to receive a first input voltage signal. A second path includes at least the transistor coupled to the word line. At least a portion of the second path is embedded within the first path. The second path is coupled to receive a second input voltage signal.