Flash Memory Pillar Patterns Shield Floating Gate Coupling

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Solution Overview

Problem

In NAND flash memory devices, the increasing inter-floating gate coupling capacitance due to higher integration densities leads to malfunctioning cell transistors during read operations, and existing etching processes for forming control gate extensions are difficult to control, potentially damaging the tunnel dielectric layer.

Innovation Solution

A method of fabricating NAND flash memory devices involving the formation of pillar patterns within an isolation layer, with control gate electrodes extending between floating gates and formed above pillar patterns, reducing parasitic coupling capacitance by shielding electric fields between adjacent floating gates.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If higher integration density is implemented in NAND flash memory devices, then storage capacity increases, but inter-floating gate coupling capacitance increases causing cell transistor malfunction

Engineering Contradiction:

Improveintegration densityVSAvoidcell transistor operation

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

A control gate extension is introduced as an intermediary element between adjacent floating gates. This extension acts as a shielding structure that interrupts the electric field coupling between neighboring floating gates, thereby reducing parasitic coupling capacitance while allowing higher integration density to be maintained without cell transistor malfunction

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If conventional etching processes are used to form control gate extensions, then device structure is modified to reduce capacitance, but tunnel dielectric layer may be damaged

Engineering Contradiction:

Improveparasitic coupling capacitance reductionVSAvoidtunnel dielectric layer damage

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The etching process parameters are optimized and modified to achieve selective removal of the isolation layer without damaging the tunnel dielectric layer. By controlling etching depth, time, and chemical composition, the control gate extension is formed with precise dimensional control, reducing parasitic capacitance while preventing harmful damage to the tunnel dielectric layer

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS7554149B2Flash memory devices comprising pillar patterns and methods of fabricating the same

Publication Date: 2009.06.30 SAMSUNG ELECTRONICS CO LTD

AI summary

Flash memory devices include pillar patterns formed between selected pairs of floating gates and control gate extensions that penetrate between selected pairs of floating gates are provided. Methods of fabricating the flash memory devices are also provided.