Flash Storage Plug-In Architecture for Heterogeneous SSD Updates

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Solution Overview

Problem

Updating storage architectures to accommodate different generations, versions, and manufacturers of flash memory and heterogeneous combinations poses logistical and metadata management challenges.

Innovation Solution

Implementing a direct-mapped flash storage system where the operating system directly addresses data blocks without translation by storage controllers, offloading device management responsibilities to storage array controllers, and utilizing non-volatile RAM as a buffer to improve latency and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If storage architectures are updated to accommodate different generations, versions, and manufacturers of flash memory, then adaptability is improved, but device complexity and metadata management challenges increase

Engineering Contradiction:
ImproveadaptabilityVSAvoiddevice complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent implements a universal storage architecture where the storage array controller serves multiple functions: it manages heterogeneous flash memory devices from different manufacturers and generations, handles metadata operations, and provides a unified interface to the host. This multi-functional controller design allows the system to accommodate various flash memory types without requiring separate management systems for each device type, thereby improving adaptability while controlling complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If storage array controllers manage all device operations, then adaptability to different flash memory is improved, but write operations increase and efficiency decreases

Engineering Contradiction:
ImproveadaptabilityVSAvoidefficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent segments the storage management functions by separating the host system from the storage array controller, which in turn manages individual flash memory devices. This segmentation allows the controller to handle device-specific operations locally without requiring continuous host intervention, reducing unnecessary write operations and improving overall system efficiency while maintaining adaptability to different device types.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The storage array controller is designed to autonomously manage flash memory devices without requiring constant host system involvement. The controller performs self-service operations including device initialization, data mapping, and error handling, which reduces the number of write operations initiated by the host and improves storage system efficiency while maintaining compatibility with various flash memory types.

Inventive Principle:
Principle #25Self-service

3Productivity

If direct-mapped addressing is implemented, then productivity and efficiency are improved, but reliability and latency may be affected without buffer mechanisms

Engineering Contradiction:
ImproveefficiencyVSAvoidreliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces a buffer mechanism as an intermediary between the direct-mapped addressing system and the flash memory devices. This buffer layer absorbs timing variations and ensures data integrity, allowing the system to maintain the efficiency benefits of direct addressing while improving reliability by preventing data loss during transient errors or latency variations.

Inventive Principle:
Principle #24Intermediary (Mediator)

Data Source

PatentUS20260086951A1Updates for differing flash storage devices of a storage system
Publication Date: 2026.03.26 PURE STORAGE INC
  • US20260086951A1 patent drawing
  • US20260086951A1 patent drawing
  • US20260086951A1 patent drawing

AI summary

A method of operating a storage system is provided. The method includes executing an operating system on one or more processors of a compute device that is coupled to one or more solid-state drives and executing a file system on the one or more processors of the compute device. The method includes configuring the compute device with one or more replaceable plug-ins that are specific to the one or more solid-state drives, and executing a flash translation layer on the one or more processors of the compute device, with assistance through the one or more replaceable plug-ins for reading and writing the one or more solid-state drives.