Embedded Flash Power Sequencing for Synchronized Supply Ramp-Up

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Solution Overview

Problem

Prior art embedded flash memory systems experience inconsistencies in power sequencing, leading to operational issues where voltage levels for VDD and VDDFLASH do not synchronize properly during power-up and power-down sequences, causing logic circuits to malfunction due to incomplete readiness of other circuits.

Innovation Solution

A revised power management unit that generates improved power sequencing by synchronizing the ramp-up and ramp-down of voltage sources VDD, VDDFLASH, and VDDCORE, using NMOS and PMOS source follower circuits and diode connections to ensure simultaneous voltage levels during power states, and employing precision regulation circuits to stabilize core logic voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If independent power sequencing is used for VDD and VDDFLASH, then each voltage can be controlled independently, but voltage synchronization between VDD and VDDFLASH deteriorates causing operational inconsistencies

Engineering Contradiction:

ImproveIndependent voltage controlVSAvoidPower sequencing synchronization

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

A dedicated power sequencing circuit is introduced as an intermediary component between the power sources and the circuits they supply. This circuit monitors and coordinates the ramp-up and ramp-down of VDD and VDDFLASH voltages, ensuring they reach operational levels simultaneously and maintain synchronized states throughout operation, thereby resolving the synchronization issue while preserving independent control capabilities.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Speed

If VDD reaches operational level before VDDFLASH, then logic circuits can start functioning earlier, but circuit contention and malfunction occur due to incomplete readiness of flash-related circuits

Engineering Contradiction:

ImprovePower-up speedVSAvoidCircuit operation stability

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The power sequencing circuit performs preliminary actions by pre-coordinating and preparing the power delivery sequence. It ensures that VDDFLASH and its associated circuits are ready to operate simultaneously with VDD by controlling the timing and rate of voltage ramp-up, preventing premature operation of logic circuits that would otherwise cause contention and malfunction.

Inventive Principle:

Principle #10Preliminary action

3Loss of time

If rapid power-up sequencing is implemented, then system initialization is faster, but voltage synchronization and stability deteriorate causing operational issues

Engineering Contradiction:

ImprovePower-up timeVSAvoidVoltage synchronization stability

Core Design Contradiction:

Loss of timeVSStability of the object's composition

Solution Approach 1:

The power sequencing circuit implements dynamic control of the power-up process, continuously monitoring voltage levels and adjusting the ramp-up rate in real-time. This dynamic adjustment allows the system to achieve fast initialization while maintaining voltage synchronization and stability, as the circuit can accelerate voltage rise when synchronization is maintained and slow down when approaching critical thresholds.

Inventive Principle:

Principle #15Dynamics

Data Source

PatentEP3416168B1Improved power sequencing for embedded flash memory devices

Publication Date: 2019.12.25 SILICON STORAGE TECHNOLOGY INC

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AI summary

A system and method for improved power sequencing within an embedded flash memory device is disclosed.