Embedded Flash Power Sequencing for Synchronized Voltage Ramp-Up

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Prior art embedded flash memory systems experience inconsistencies in power sequencing, leading to inefficient operation due to voltage sources not reaching sufficient levels simultaneously during power-up and power-down sequences, causing logic circuits to malfunction.

Innovation Solution

A power management unit that synchronizes the ramp-up and ramp-down sequences of multiple voltage sources (VDD, VDDFLASH, and VDDCORE) to ensure simultaneous reaching of operating levels, using NMOS and PMOS source follower circuits and precision regulation to maintain stable voltage levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If voltage sources ramp up independently during power-on sequence, then each voltage source can reach its operating level at different times, but this causes logic circuits to malfunction due to inconsistent power states

Engineering Contradiction:

Improvelogic circuit operation reliabilityVSAvoidpower sequencing control complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The power management unit performs preliminary actions by pre-coordinating the ramp-up and ramp-down sequences of multiple voltage sources. The system establishes a predetermined power sequence where VDD, VDDFLASH, and VDDCORE are controlled to reach and leave operational levels in a specific order, preventing logic circuit malfunctions before they can occur during independent voltage transitions.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The power management unit implements feedback mechanisms to monitor the status of multiple voltage sources and dynamically adjust their ramp-up and ramp-down sequences. This feedback control ensures that voltage sources reach operational levels simultaneously and maintains consistent power states across the system, resolving the contradiction between reliability and control complexity.

Inventive Principle:

Principle #23Feedback

2Productivity

If voltage sources are synchronized to reach operational levels simultaneously, then power efficiency is improved and circuit malfunctions are prevented, but this requires complex power sequencing control

Engineering Contradiction:

Improvepower efficiencyVSAvoidpower management unit complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the control of multiple independent voltage sources into a single integrated power management unit. This consolidation synchronizes the ramp-up and ramp-down sequences of VDD, VDDFLASH, and VDDCORE, ensuring they reach and leave operational levels simultaneously. The merging approach improves power efficiency by preventing partial operation states while managing the inherent control complexity through integration.

Inventive Principle:

Principle #5Merging (Combining)

3Stability of the object's composition

If voltage sources operate independently during power-down sequence, then control is simpler, but this causes voltage sources to leave operational levels at different times leading to system inconsistencies

Engineering Contradiction:

Improvesystem state consistencyVSAvoidpower sequencing coordination complexity

Core Design Contradiction:

Stability of the object's compositionVSDevice complexity

Solution Approach 1:

The power management unit establishes a predetermined power-down sequence in advance, coordinating when each voltage source (VDD, VDDFLASH, VDDCORE) will leave its operational level. This preliminary coordination ensures that all voltage sources transition together, maintaining system state consistency and preventing the inconsistencies that would arise from independent voltage source operation during power-down.

Inventive Principle:

Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This solution ensures that all voltage sources reach operational levels simultaneously during power-up and power-down, preventing circuit malfunctions and improving power efficiency by maintaining consistent states across the embedded flash memory system.

Implementation Method 1

A power management unit that synchronizes the ramp-up and ramp-down sequences of multiple voltage sources (VDD, VDDFLASH, and VDDCORE) to ensure simultaneous reaching of operating levels

Methodology Applied

Scientific EffectSynchronization:

Implementation Method 2

using NMOS and PMOS source follower circuits and precision regulation to maintain stable voltage levels

Methodology Applied

Scientific EffectVoltage regulation:

Implementation Method 3

a first voltage source for providing a first power supply voltage utilized in performing program, erase, and read operations in flash memory cells

Methodology Applied

Scientific EffectElectrical power supply:

Data Source

PatentEP3149731B1Improved power sequencing for embedded flash memory devices

Publication Date: 2018.09.26 SILICON STORAGE TECHNOLOGY INC

Figure 1
Figure 2
Figure 3

AI summary

A system and method for improved power sequencing within an embedded flash memory device is disclosed.