Flash Memory Power State Sequencing for Lower Transition Latency
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory systems experience high latency during power state transitions, particularly when transitioning from a higher-power state to a non-operational state, which can be reduced by efficiently managing power state transitions to minimize total latency.
Innovation Solution
A memory controller determines whether the current power state is higher than a threshold state and transmits a command to transition to the threshold power state before entering a non-operational state, thereby reducing latency by transitioning through an intermediate power state with shorter exit times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the memory system transitions directly from a higher-power state to a non-operational power state, then the power state transition is completed in one step, but the total latency is high due to long exit times from higher-power states
Solution Approach 1:
The power state transition is segmented into multiple intermediate steps. Instead of transitioning directly from a higher-power state to a non-operational state, the system transitions through one or more intermediate power states with progressively shorter exit times, thereby reducing the total latency of the transition process
Solution Approach 2:
The system performs preliminary action by pre-determining the exit times of different power states and pre-planning the transition path. The controller identifies which intermediate power states to pass through before entering the non-operational state, optimizing the transition sequence in advance to minimize total latency
2Loss of time
If the memory system uses multiple power states with different exit times, then the latency can be optimized by selecting appropriate intermediate states, but the control logic becomes more complex
Solution Approach 1:
The controller uses feedback by continuously monitoring the current power state and comparing it with the target non-operational state. Based on the monitored exit times of different power states, the controller dynamically adjusts the transition path, selecting intermediate power states that optimize the total transition latency while managing control logic through adaptive decision-making
Data Source
AI summary
This disclosure provides systems, methods, and devices for memory systems that support improved power state transition. In a first aspect, a method of accessing data in a flash memory system includes a controller configured to perform operations including: determining a power state transition of the memory system to a non-operational power state; determining, after determining the power state transition, whether a current power state is a higher-power state than a threshold power state; and transmitting, after determining the current power state is the higher-power state than the threshold power state, a first command to the memory system to transition to the threshold power state before the memory system transitions to the non-operational power state. Other aspects and features are also claimed and described.