Non-Volatile Memory Pulse Sequencing for Precise Program Levels
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing storage devices face inefficiencies in programming non-volatile memory cells due to the lack of a systematic approach to determine the optimal program pulse levels and verification processes, leading to suboptimal performance and reliability.
Innovation Solution
A control circuit in the storage device applies a series of program and verification pulses with incremental or decremental steps, determining the program-permission mode based on logical operations between current and target program levels, optimizing the programming process for non-volatile memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional programming methods are used without systematic determination of optimal program pulse levels, then the programming process is simple, but programming efficiency and reliability are suboptimal
Solution Approach 1:
The control circuit performs verification operations after program pulse application to check whether memory cells are properly programmed. Based on verification results, the control circuit determines program-permission mode or program-inhibition mode for subsequent pulses, creating a feedback loop that optimizes programming efficiency while managing complexity through systematic control
Solution Approach 2:
The control circuit applies a series of program pulses with different levels (incremental or decremental steps) to memory cells. By systematically varying the program pulse levels and determining optimal sequences based on verification results, the system achieves high programming efficiency and reliability through controlled parameter changes
2Manufacturing precision
If multiple program pulses with different levels are applied to program memory cells, then programming precision is improved, but the time required for programming increases
Solution Approach 1:
The control circuit determines in advance which memory cells should be in program-permission mode and which in program-inhibition mode for each pulse application operation. This preliminary determination allows the system to apply multiple pulses with different levels efficiently, achieving high precision while minimizing time by avoiding unnecessary operations
Solution Approach 2:
The control circuit applies program pulses selectively to only those memory cells that need programming based on the determined mode. By using partial action (only programming cells that require it) rather than excessive action (programming all cells regardless of state), the system achieves precise programming with optimized time consumption
3Reliability
If verification operations are performed after each program pulse application, then programming reliability is improved, but the total number of operations increases
Solution Approach 1:
The control circuit performs verification operations after program pulse application to check programming status. Based on verification feedback, the control circuit determines whether to apply further pulses or inhibit programming for subsequent operations. This feedback mechanism ensures high reliability while optimizing throughput by avoiding redundant operations on already-programmed cells
4Measurement precision
If program-permission mode and program-inhibition mode are systematically determined through logical operations, then programming accuracy is improved, but control complexity increases
Solution Approach 1:
The control circuit uses logical operations to determine program-permission mode or program-inhibition mode based on comparisons between current program levels and target program levels. By systematically changing control parameters (mode determination) based on clear logical conditions, the system achieves high accuracy while managing complexity through structured decision-making logic
Data Source
AI summary
A storage device includes a group of non-volatile memory cells, page buffers coupled to the non-volatile memory cells and a control circuit. The control circuit performs one or more program loops on the group according to program data loaded on the page buffers, each of the program loops include a series of consecutive program pulse application operations and a series of consecutive verification operations.


