Multi-Stage Flash Programming via Host Buffering
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Solution Overview
Problem
Multi-Level Cell (MLC) flash memory devices require multiple stages of programming across adjacent word lines, necessitating temporary storage capacity in latches, which increases manufacturing costs and latency due to repeated data transfer during write operations.
Innovation Solution
The data storage device receives multiple copies of write commands from a host device, associating each copy with a stage of the multi-stage programming operation, allowing it to perform programming without needing temporary storage capacity between stages, by retrieving data directly from the host device at each stage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If data is stored in temporary storage capacity (RAM) to support multi-stage write operations, then the data storage device can perform programming operations, but the manufacturing cost increases
Solution Approach 1:
The patent extracts the temporary storage function from the flash memory die by moving data buffering to the host device. The host device's RAM serves as the temporary storage, allowing the flash memory die to eliminate or reduce its own temporary storage capacity while still supporting multi-stage write operations.
Solution Approach 2:
The patent introduces the host device as an intermediary between the data to be written and the flash memory die. The host device buffers data in its RAM and transfers it to the flash memory die in stages, eliminating the need for large temporary storage capacity in the flash memory die itself.
2Productivity
If data is repeatedly transferred to latches during multiple write stages, then programming can be completed, but latency increases
Solution Approach 1:
The patent applies preliminary action by having the host device prepare and buffer all necessary data in its RAM before the flash memory die begins programming operations. This allows the flash memory die to receive data continuously without repeated transfer delays, as the data is already staged and ready for programming.
Solution Approach 2:
The host device creates a copy of the data in its RAM that can be referenced throughout the multi-stage programming process. This copy serves as a local buffer that eliminates the need for repeated data transfers between the host and flash memory die, reducing latency while maintaining data availability for all programming stages.
3Adaptability or versatility
If sufficient temporary storage capacity is provided in the flash memory die, then multi-stage write operations can proceed, but device complexity and cost increase
Solution Approach 1:
The patent extracts the temporary storage function from the flash memory die architecture and relocates it to the host device. This extraction simplifies the flash memory die design by removing the need for large latch arrays or intermediate buffers, while the host device's existing RAM provides the necessary temporary storage capability.
Solution Approach 2:
The patent leverages the host device's RAM for a dual purpose: general-purpose data buffering and specific temporary storage for flash memory programming operations. This multi-functionality eliminates the need for dedicated temporary storage structures in the flash memory die, reducing device complexity while maintaining multi-stage write capability.
Data Source
AI summary
An apparatus includes a memory storing a group of pages of data. An interface of the apparatus is configured to send, to a data storage device (DSD) from a first command queue, a first instruction of instructions to store the group of pages to the DSD using a logical address corresponding to the group of pages. The interface is further configured to send, to the DSD from a second command queue, a second instruction of the instructions to write the group of pages to the DSD using the logical address. Sending a first copy of the group of pages in association with the first instruction and sending a second copy of the group of pages in association with the second instruction enables a multi-stage programming operation to be performed at the DSD without storing the group of pages at the DSD between stages of the multi-stage programming operation.