Secure Flashing via Main Processor Offloading

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Solution Overview

Problem

Secondary processors in vehicle electronic control units (ECUs) lack sufficient computing power and memory to perform secure flashing operations due to the resource-intensive nature of asymmetric digital key cryptography, limiting the security of programming these controllers.

Innovation Solution

Distribute processing duties between a main processor and a secondary processor, where the main processor performs the decryption, hashing, and validation steps for secure flashing, allowing the secondary processor to receive validated content without needing to perform these operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If asymmetric key cryptography is used for secure flashing, then security and authenticity verification are improved, but computing power and memory requirements increase

Engineering Contradiction:
ImprovesecurityVSAvoidcomputing power
Core Design Contradiction:
ReliabilityVSPower

Solution Approach 1:

The patent divides the ECU into a main processor and one or more secondary processors. The main processor handles the computationally intensive asymmetric key cryptography operations (decryption and hash verification), while secondary processors handle other control functions. This segmentation allows secure flashing to be performed without overloading the limited resources of secondary processors.

Inventive Principle:
Principle #1Segmentation

2Reliability

If asymmetric key cryptography is used for secure flashing, then security and authenticity verification are improved, but memory space requirements increase

Engineering Contradiction:
ImprovesecurityVSAvoidmemory space
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent segments memory resources between main and secondary processors. The main processor contains the necessary memory for buffering large algorithms and storing public keys required for asymmetric cryptography, while secondary processors have reduced memory allocations for their specific control functions.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If processing duties are centralized in the main processor, then security operations are simplified, but the main processor's workload increases

Engineering Contradiction:
Improveprocessing architectureVSAvoidmain processor workload
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements a bootloader on the main processor that performs preliminary security verification of content files before they are transferred to secondary processors. This preliminary action includes verifying digital signatures and hash values, ensuring that only authenticated content is processed further, thereby simplifying the overall security architecture.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS8856538B2Secured flash programming of secondary processor
Publication Date: 2014.10.07 GM GLOBAL TECHNOLOGY OPERATIONS LLC
  • US8856538B2 patent drawing
  • US8856538B2 patent drawing
  • US8856538B2 patent drawing

AI summary

A system and method for securely flashing a controller, where the controller includes at least one main processor and at least one secondary processor, and where the processing duties are distributed between the processors. A programming tool provides a content file to be flashed and a digital signature to the controller. The controller calculates a hash value of the content file, decrypts the digital signature using a public key to generate a decrypted hash value, compares the decrypted hash value to the calculated hash value, and determines that the content file is valid if the decrypted hash code matches the calculated hash value, where one or more of the steps of calculating the hash value, decrypting the digital signature, comparing the decrypted hash value to the calculated hash value and determining that the content file is valid, is performed by the main processor for the secondary processor.