Flash Memory Programming Levels for Lower Sector Error Rates
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Flash memory devices experience increased sector error rates due to threshold voltage drops in multi-level cell (MLC) flash memory, where programmed cells falling below zero volts become harder to decode, leading to dominant error rates.
Innovation Solution
The method involves up-shifting the voltage distributions of programming levels by increasing corresponding program verify voltage levels, optimizing the tradeoff between reducing L1/L0 read errors and increasing errors for other levels, while minimizing the overall sector error rate by adjusting program verify thresholds to balance error rate probabilities between MSB and LSB page reads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If program verify levels are increased to up-shift voltage distributions and prevent cells from falling below zero volts, then sector error rate decreases, but bit error rate increases due to increased overlap between adjacent programming levels
Solution Approach 1:
The patent changes the program verify level parameters to up-shift voltage distributions. Specifically, it increases the program verify levels (e.g., PV0 and PV1) to shift the programming distributions (L1 and L2) upward, preventing cells from falling below zero volts and reducing sector errors, while accepting increased bit errors from distribution overlap
Solution Approach 2:
The patent applies prior cushioning by proactively increasing program verify levels before threshold voltage drops cause excessive sector errors. The controller anticipates voltage drift and adjusts program verify levels in advance to maintain adequate separation between programming distributions, cushioning against future error rate increases
2Reliability
If program verify levels are adjusted to optimize the tradeoff between sector error rate and bit error rate, then overall device reliability is improved, but programming complexity increases
Solution Approach 1:
The patent implements feedback by having the controller monitor error rates and adjust program verify levels accordingly. The controller receives feedback about threshold voltage drift and programming distribution overlap, then dynamically adjusts program verify levels to optimize the tradeoff between sector errors and bit errors, improving overall reliability while managing complexity through adaptive control
Data Source
AI summary
The subject disclosure describes a method for reducing a sector error rate in a flash memory device, the method comprising, identifying a first program verify level having a first value, selecting an adjustment value for the first program verify level and programming the adjustment value to the first program verify level to replace the first value and to shift a first programming distribution associated with the first program verify level, wherein the shift in the first programming distribution is associated with a decrease in a sector error rate, wherein the shift in the first programming distribution is associated with an increase in a bit error rate. A flash storage device and computer-readable media are also provided.