Multi-Level Flash Programming With Multiphase Gray Code Mapping

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Solution Overview

Problem

Existing methods for programming multi-level flash memory cells, such as foggy-fine programming, require additional hardware resources and increase complexity and cost, limiting capacity, endurance, and performance due to the need for intermediate buffers and lower storage density.

Innovation Solution

Implementing an optimized multiphase mapping with a balanced Gray code to transition from a first programming phase to a second phase, minimizing average voltage change and eliminating the need for intermediate buffers by allowing direct read and write operations, thereby simplifying device design and improving performance metrics.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If foggy-fine programming is used to program multi-level cells, then programming precision is improved, but device complexity increases due to additional hardware resources and intermediate buffers

Engineering Contradiction:
Improveprogramming precisionVSAvoiddevice complexity
Core Design Contradiction:
Manufacturing precisionVSDevice complexity

Solution Approach 1:

The patent extracts and eliminates the intermediate buffer component from the programming system. By using a multiphase mapping approach where data is directly mapped from MLC states to QLC states without requiring temporary storage, the intermediate buffer is removed, reducing device complexity while maintaining programming precision through the optimized mapping algorithm

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent uses a mapping table that copies state information from MLC to QLC phases. The mapping table stores the relationship between MLC states and corresponding QLC states, allowing the system to determine target states through table lookup rather than requiring complex real-time calculations or intermediate storage, thus simplifying the hardware architecture

Inventive Principle:
Principle #26Copying

2Manufacturing precision

If foggy-fine programming is used to program multi-level cells, then programming precision is improved, but storage capacity decreases due to lower storage density

Engineering Contradiction:
Improveprogramming precisionVSAvoidstorage capacity
Core Design Contradiction:
Manufacturing precisionVSQuantity of substance

Solution Approach 1:

The patent transitions from a two-phase programming approach (foggy then fine) to a multiphase mapping approach that operates in the state-space dimension. By defining direct mapping relationships between MLC states and QLC states in a state transition table, the system achieves precise programming without requiring intermediate buffer storage, thereby increasing effective storage capacity

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent changes the programming parameters by using optimized mapping tables that define precise voltage threshold relationships between MLC and QLC states. This parameter optimization allows direct programming with high precision while maximizing the number of usable states per cell, thereby increasing storage capacity

Inventive Principle:
Principle #35Parameter changes

3Reliability

If intermediate buffers are used in programming multi-level cells, then programming reliability is improved, but device complexity increases

Engineering Contradiction:
Improveprogramming reliabilityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements a self-service mechanism where the mapping table itself contains all necessary information for reliable state transitions. The mapping table is designed to account for voltage drift and threshold variations, allowing the system to self-correct and maintain reliability without external intermediate buffers or additional control hardware

Inventive Principle:
Principle #25Self-service

Solution Approach 2:

The patent introduces a mapping table as a software-based intermediary that replaces hardware intermediate buffers. The mapping table mediates between MLC input states and QLC output states, providing reliable state transitions through pre-calculated mapping relationships while requiring minimal hardware resources

Inventive Principle:
Principle #24Intermediary (Mediator)

4Manufacturing precision

If additional hardware resources are allocated for programming multi-level cells, then programming precision is improved, but available space for productive uses decreases

Engineering Contradiction:
Improveprogramming precisionVSAvoidavailable device space
Core Design Contradiction:
Manufacturing precisionVSArea of stationary object

Solution Approach 1:

The patent extracts and removes intermediate buffer hardware from the device architecture. By using a multiphase mapping approach that operates directly on the memory cells without temporary storage requirements, the patent eliminates the need for dedicated buffer regions, thereby increasing available storage space while maintaining programming precision through software-based mapping tables

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11107522B2Multi-level cell programming using optimized multiphase mapping with balanced gray code
Publication Date: 2021.08.31 SANDISK TECHNOLOGIES LLC
  • US11107522B2 patent drawing
  • US11107522B2 patent drawing
  • US11107522B2 patent drawing

AI summary

Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.