Flash Memory Pseudo Pass Detector for Programming Pulse Minimization
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Solution Overview
Problem
Conventional flash memory devices face challenges in correcting a large number of data bit errors in each row of memory cells, leading to the need for excessive programming pulses, which can result in data corruption and inefficiency.
Innovation Solution
The implementation of a pseudo pass detector that compares data signals in subsets and uses analog or digital logic to determine when the number of errors is within the correction capacity of ECC circuitry, allowing for reduced programming pulses and improved error correction.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional programming methods are used to program all rows of memory cells, then complete programming coverage is achieved, but the number of programming pulses becomes excessively large causing data corruption and inefficiency
Solution Approach 1:
The memory array is divided into multiple rows, and the programming process segments these rows into different groups. First programming pulses are applied to program a first group of rows, then verify and identify pass rows. Subsequently, second programming pulses are applied to program a second group of rows excluding the identified pass rows. This segmentation allows efficient programming while reducing total pulse count.
Solution Approach 2:
A verify operation is performed after applying first programming pulses to identify pass rows (rows that have been successfully programmed). This feedback information is used to determine which rows should receive second programming pulses, enabling intelligent programming decisions that reduce unnecessary pulses and improve overall programming efficiency.
2Manufacturing precision
If multiple programming pulses are applied to ensure complete programming, then programming coverage improves, but data corruption increases due to excessive pulses
Solution Approach 1:
The verify operation is performed as a preliminary action after first programming pulses to identify rows that have been successfully programmed (pass rows). This preliminary identification prevents subsequent programming pulses from being applied to already programmed rows, thereby avoiding data corruption while ensuring complete programming coverage for remaining rows.
Solution Approach 2:
Instead of applying programming pulses uniformly to all rows, the method applies second programming pulses only to specific rows that were not identified as pass rows during verification. This partial action approach ensures complete programming coverage while minimizing excessive pulses that could cause data corruption.
3Productivity
If programming pulses are reduced to improve efficiency, then programming speed increases, but error correction capability may be compromised
Solution Approach 1:
The verify operation provides feedback on programming status, identifying pass rows that have been successfully programmed. This feedback enables the system to reduce the number of programming pulses by excluding pass rows from subsequent programming operations, thereby improving programming speed while maintaining reliability through targeted programming of only necessary rows.
Solution Approach 2:
The method changes the programming parameter strategy by applying different programming pulse sequences to different row groups. First programming pulses are applied to all rows initially, then second programming pulses are applied selectively to non-pass rows. This parameter change optimizes both programming speed and error correction capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of programming pulses required and enhances the ability to correct data bit errors, minimizing data corruption and optimizing programming efficiency.
Implementation Method 1
A floating gate, typically made of doped polysilicon, is disposed over the channel region and is electrically isolated from the channel region by a layer of gate oxide. A control gate is fabricated over the floating gate, and it can also be made of doped polysilicon. The control gate is electrically separated from the floating gate by a dielectric layer.
Implementation Method 2
For example, a negative charge can be placed on the floating gate by grounding the source while applying a sufficiently large positive voltage to the control gate to attract electrons, which tunnel through the gate oxide to the floating gate from the channel region.
Implementation Method 3
As negative charge is added to the floating gate, the threshold voltage of the flash memory cell increases. During a read operation, a read voltage is applied to the control gate that is large enough to render the cell conductive if no charge is stored on the floating gate, but not large enough to render the cell conductive if charge is stored on the floating gate.
Data Source
AI summary
A flash memory device programs cells in each row in a manner that minimizes the number of programming pulses that must be applied to the cells during programming. The flash memory device includes a pseudo pass circuit that determines the number of data errors in each of a plurality of subsets of data that has been programmed in the row. The size of each subset corresponds to the number of read data bits coupled from the memory device, which are simultaneously applied to error checking and correcting circuitry. During iterative programming of a row of cells, the pseudo pass circuit indicates a pseudo pass condition to terminate further programming of the row if none of the subsets of data have a number of data errors that exceeds the number of data errors that can be corrected by the error checking and correcting circuitry.