Dynamic Flash Quantizer Windowing for Low-Power Delta-Sigma ADCs
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Solution Overview
Problem
Multibit flash quantizer circuits in delta-sigma ADCs face high power consumption and 'kickback' noise issues, limiting their efficiency and input slew rate handling capabilities.
Innovation Solution
Implementing a dynamically-configurable flash quantizer circuit that uses power control signals to place a subset of comparator circuits in a reduced power state based on previous quantizer output codes, allowing for significant power savings while maintaining full resolution conversion capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If all comparator circuits are kept in active state to maintain full resolution conversion capability, then measurement precision is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamic power management by making the comparator circuits transition between active and reduced power states based on signal conditions. The quantizer circuit dynamically adjusts the number of active comparators according to the input signal characteristics, allowing the system to maintain measurement precision when needed while reducing power consumption during normal operation.
Solution Approach 2:
The patent changes the operational state parameter of the comparator circuits from a static all-active configuration to a dynamic configuration where comparators can be switched between active and reduced power states. This parameter change enables the system to adapt power consumption levels while maintaining the capability for full resolution conversion when required.
2Speed
If more comparator circuits are activated to handle higher input slew rates, then speed is improved, but power consumption increases
Solution Approach 1:
The system dynamically adjusts the number of active comparator circuits based on the input signal's slew rate requirements. When high input slew rates are detected, additional comparators are activated to handle the faster signal changes. When lower slew rates are present, fewer comparators remain active, reducing power consumption while maintaining adequate performance.
Solution Approach 2:
The patent employs partial action by activating only the necessary number of comparator circuits required to handle the current input signal conditions. Instead of keeping all comparators continuously active, the system activates just enough comparators to maintain performance, thereby reducing overall power consumption while preserving the capability to handle higher slew rates when needed.
3Use of energy by moving object
If a subset of comparator circuits is placed in reduced power state to save power, then power consumption is reduced, but measurement precision may deteriorate
Solution Approach 1:
The patent implements feedback mechanisms that monitor the input signal characteristics and the output of the quantizer circuit. Based on this feedback, the control logic determines whether to activate additional comparator circuits to maintain full resolution capability. This feedback ensures that measurement precision is maintained when signal conditions require it, while allowing power savings when the full resolution capability is not needed.
Solution Approach 2:
The system prepares by maintaining the capability to quickly activate additional comparator circuits when needed. The control logic is pre-configured to respond to signal conditions that require full resolution, allowing the system to transition from reduced power state to full performance state without significant delay, thus preventing precision deterioration when high-precision conversion is required.
4Use of energy by moving object
If dynamically-configurable quantizer circuit is implemented to reduce power, then power consumption is reduced, but device complexity increases
Solution Approach 1:
The patent segments the quantizer circuit into multiple independent comparator circuits that can be individually controlled. This segmentation allows the system to activate only the necessary subset of comparators based on power management requirements. The segmented architecture, while adding some control complexity, enables fine-grained power management and maintains modularity that simplifies the overall design.
Data Source
AI summary
A multibit flash quantizer circuit, such as included as a portion of delta-sigma conversion circuit, can be operated in a dynamic or configurable manner. Information indicative of at least one of an ADC input slew rate or a prior quantizer output code can be used to establish a flash quantizer conversion window. Within the selected conversion window, comparators in the quantizer circuit can be made active. Comparators outside the conversion window can be made dormant, such as depowered or biased to save power. An output from such dormant converters can be preloaded and latched. In this manner, full resolution is available without requiring that all comparator circuits within the quantizer remain active at all times.