Flash Memory RAID Buffer Layout for Temporary Parity Updates
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Solution Overview
Problem
The frequent exchange of parities between the RAID buffer and DRAM during RAID encoding in flash memory controllers affects the efficiency of the encoder due to the limited space in the RAID buffer.
Innovation Solution
A method and controller that configures a flash memory module with a super block structure, encodes data to generate temporary parities, and stores them in a buffer with specific areas, allowing only a portion of temporary parities to be stored in certain areas, reducing the need for parity movement between the RAID buffer and DRAM.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the RAID buffer space is limited, then the encoder cannot store all temporary parities, but frequent exchange between RAID buffer and DRAM reduces encoding efficiency
Solution Approach 1:
The patent segments the buffer into two distinct parts: a first part (RAID buffer) for storing temporary parities that need frequent access, and a second part (DRAM) for storing temporary parities that do not need frequent access. This segmentation allows the system to maintain high encoding efficiency by keeping actively used parities in the fast RAID buffer while utilizing the larger DRAM capacity for less frequently accessed parities, thus resolving the contradiction between limited buffer space and encoding efficiency.
2Quantity of substance
If all temporary parities are stored in DRAM, then sufficient storage space is available, but access speed and encoding efficiency decrease
Solution Approach 1:
The patent applies local quality by assigning different storage locations to temporary parities based on their access patterns. The first part of the buffer (RAID buffer) provides fast access speed for temporary parities that need frequent retrieval during encoding, while the second part (DRAM) provides sufficient storage capacity for all temporary parities. This localized optimization of storage characteristics resolves the contradiction between storage capacity and access speed.
Data Source
AI summary
The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: configuring the flash memory module to have a super block, wherein the super block comprises a plurality of blocks respectively located in a plurality of dies; encoding M data respectively to sequentially generate M temporary parities, wherein M is a positive integer greater than two; storing the M temporary parities into N areas of a buffer sequentially, wherein N is less than M, each of the N areas is only allowed to store one temporary parity, and a first part of the N areas is always used to store a portion temporary parities of the M temporary parities and their subsequent updated temporary parities; and generating M parities according to the M temporary parities, respectively, and writing the M parities into the super block.