Flash Memory Rank Modulation with Minimum Push-Up Coding
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Solution Overview
Problem
Flash memories face limitations in speed, reliability, and storage capacity due to quality degradation from block erasures, slow writing speeds, and errors caused by charge leakage and other factors, which restrict their longevity and performance.
Innovation Solution
The implementation of a minimum push-up scheme and multi-permutation coding in flash memories, where data is stored by programming rank locations with a minimum cell differentiation amount and using multi-cells and permutations to efficiently manage charge levels, reducing the need for block erasures and enhancing storage capacity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conservative cell-programming process is used to avoid over-programming errors, then data reliability is improved, but writing speed becomes ten times slower than reading
Solution Approach 1:
The patent segments the programming process into multiple stages with different verification levels. Critical data undergoes rigorous multi-stage programming and verification, while non-critical data uses faster single-stage programming. This segmentation allows the system to achieve overall high reliability without uniformly sacrificing writing speed across all data types.
Solution Approach 2:
The patent dynamically changes programming parameters such as pulse width, voltage level, and number of programming cycles based on the importance of the data being written. High-priority data receives more aggressive programming parameters with additional verification steps, while low-priority data uses streamlined parameters for faster writing, thus resolving the contradiction between reliability and speed.
2Reliability
If block erasure is performed to correct over-programming errors, then data reliability is restored, but the flash memory lifetime decreases due to limited erasure endurance
Solution Approach 1:
The patent performs preliminary verification and correction actions during the programming process itself, detecting and correcting potential over-programming errors before they require block erasure. This includes intermediate read-verify cycles and adaptive programming that stops before over-programming occurs, thereby preserving flash memory lifetime while maintaining data reliability.
Solution Approach 2:
The patent converts the harmful effect of charge leakage and disturbance, which traditionally cause errors requiring erasure, into a beneficial monitoring opportunity. By continuously monitoring charge levels and using the natural charge distribution patterns, the system can detect and correct errors in-situ without erasure, turning a reliability threat into a diagnostic advantage that extends memory lifetime.
3Quantity of substance
If multi-level cells are used to increase storage capacity, then storage capacity is improved, but errors caused by charge leakage and disturbs become more common
Solution Approach 1:
The patent implements nested error correction codes where multiple layers of redundancy are embedded within the data structure. Outer codes protect against charge leakage over long periods, while inner codes handle shorter-term disturbance errors. This nested approach allows multi-level cells to achieve high storage capacity while maintaining reliability through hierarchical error protection.
Solution Approach 2:
The patent employs continuous feedback mechanisms where stored data is periodically read and verified, and correction actions are automatically applied based on detected errors. The system adjusts programming strength and verification frequency based on feedback from charge retention monitoring, enabling multi-level cells to maintain high capacity while dynamically compensating for charge leakage and disturbance effects.
Data Source
AI summary
Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.