Flash Memory Read Decoding with Adaptive LLR Mapping
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Solution Overview
Problem
Flash memory cells experience disturbances in threshold voltage distribution due to increased program/erase cycles and retention time, leading to incorrect data retrieval when using original control gate voltage settings, necessitating a more effective read and decoding procedure.
Innovation Solution
A method and memory controller that perform error correction operations using log-likelihood ratio (LLR) mapping values, switching between different LLR mapping rules to ensure accurate data retrieval from flash memory cells, and encoding binary digits as codewords to enhance decoding capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If different control gate voltage settings are used to read the flash memory, then the possibility of obtaining correct stored information is improved, but the read time increases and more memory space is required
Solution Approach 1:
The patent changes the parameter of control gate voltage settings by using multiple different voltage levels (first, second, and third control gate voltages) to perform sequential read operations. This allows the system to adapt to threshold voltage distribution changes in flash memory cells, improving data retrieval reliability without requiring to store all intermediate results permanently
Solution Approach 2:
The patent performs preliminary read operations using different control gate voltage settings to obtain multiple sets of bit sequences before final decoding. By preparing multiple candidate readings in advance and using binary digit distribution characteristics to guide the process, the system ensures correct data retrieval while managing time and resource constraints
2Reliability
If different control gate voltage settings are used to read the flash memory, then the possibility of obtaining correct stored information is improved, but the memory space required increases
Solution Approach 1:
The patent uses parameter changes in control gate voltage settings to read the same memory location multiple times under different conditions. By analyzing binary digit distribution characteristics across these readings, the system can determine correct data values without permanently storing all intermediate results, thus improving reliability without proportionally increasing memory space requirements
Solution Approach 2:
The patent performs a limited number of read operations (first, second, and third control gate voltage settings) rather than exhaustively trying all possible voltage combinations. This partial action approach provides sufficient reliability improvement while constraining the memory space and computational resources required
3Measurement precision
If multiple read operations with different control gate voltages are performed, then data accuracy is improved, but the read time becomes longer
Solution Approach 1:
The patent employs feedback mechanisms by analyzing binary digit distribution characteristics from preliminary read operations. This feedback guides the selection and interpretation of subsequent readings, allowing the system to achieve high data accuracy while minimizing the total number of read operations required, thus reducing overall read time
Solution Approach 2:
The patent performs preliminary read operations to establish binary digit distribution characteristics before final data extraction. This preliminary action provides a foundation for accurate decoding while allowing the system to optimize the number and timing of subsequent read operations, balancing accuracy requirements with time constraints
Data Source
AI summary
An exemplary method for reading data stored in a flash memory. The method includes: controlling the flash memory to perform a read operation upon a first page of the flash memory; obtaining a first codeword of the first page; obtaining a first set of log-likelihood ratio (LLR) mapping values of the first codeword according to a first LLR mapping rule; performing an error correction operation according to the first set of LLR mapping values; obtaining a second set of LLR values of the first codeword according to a second LLR mapping rule, if the error correction operation performed according to the first set of LLR mapping values indicates an uncorrectable result; and performing the error correction operation according to the second set of LLR mapping values.