Dynamic Read Disturb Management for Flash Memory

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Solution Overview

Problem

Current memory devices face inefficiencies in managing read disturb errors, particularly due to the need for extensive system resources and latency issues caused by scanning entire blocks for localized read disturb events, which can lead to unnecessary error scanning and data relocation.

Innovation Solution

Implementing a memory controller that dynamically sets a read count threshold and scans only specific pages associated with the last read operation, relocating only valid data from affected pages to new blocks, thereby reducing resource usage and latency by managing read disturb events at a finer granularity.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the entire block is scanned for errors when read count threshold is reached, then read disturb errors are detected, but system resources are excessively consumed and latency increases

Engineering Contradiction:
Improveread disturb error detectionVSAvoidsystem resource consumption
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the error scanning process from the entire block level to the page level. Instead of scanning all pages in a block when the read count threshold is reached, the system identifies and scans only specific pages that are susceptible to read disturb errors based on their physical location and read history, thereby reducing system resource consumption while maintaining error detection capability

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent applies local quality by treating different pages within a block differently based on their susceptibility to read disturb errors. Pages adjacent to recently read pages are identified as having higher error risk and are scanned preferentially, while other pages are not scanned, creating a non-uniform error management approach that optimizes resource usage

Inventive Principle:
Principle #3Local quality

2Reliability

If the entire block is scanned for errors, then read disturb errors are detected, but latency increases due to extensive scanning

Engineering Contradiction:
Improveread disturb error detectionVSAvoiderror scanning latency
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent divides the error scanning operation into selective page-level scans rather than comprehensive block-level scans. By segmenting the scanning scope to only include pages adjacent to recently read pages, the time required for error detection is significantly reduced while maintaining adequate coverage of vulnerable areas

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent implements partial action by scanning only the necessary subset of pages that are most susceptible to read disturb errors, rather than performing exhaustive scanning of the entire block. This partial scanning approach reduces latency while still detecting the majority of read disturb errors that would occur

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If data is relocated frequently to prevent read disturb errors, then data integrity is maintained, but SRAM usage and power consumption increase

Engineering Contradiction:
Improvedata integrityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The patent implements a feedback mechanism that monitors read operations and dynamically adjusts error scanning and data relocation decisions based on actual read patterns. The system only initiates data relocation when read disturb errors are actually detected in specific pages, rather than proactively relocating data based on conservative thresholds, thereby reducing unnecessary power consumption

Inventive Principle:
Principle #23Feedback

Solution Approach 2:

The patent applies partial action by relocating data only for the specific pages that have been identified as suffering from read disturb errors, rather than relocating all data in the entire block. This selective data relocation minimizes the use of SRAM and reduces power consumption while maintaining data integrity for affected pages

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS20240054070A1A dynamic read disturb management algorithm for flash-based memory
Publication Date: 2024.02.15 MICRON TECHNOLOGY INC
  • US20240054070A1 patent drawing
  • US20240054070A1 patent drawing
  • US20240054070A1 patent drawing

AI summary

A memory device comprises a memory array and a memory controller operatively coupled to the memory array. The memory controller includes a processor configured to initiate read operations to the memory array; compare the number of rad operations to a predetermined threshold number of read operations; initiate scanning memory pages of a block of memory cells for errors in response to reaching the threshold number of read operations for the block; and iteratively change the threshold number to a new threshold number, perform the new threshold number of read operations on the block of memory cells, and error scan memory pages associated with the last read operation of the new threshold number of rad operations.