Flash Storage Read Latency Reduction via Data Reconstruction
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Solution Overview
Problem
Current storage devices based on flash chips experience significant read latency due to concurrent read, write, and erase operations, where read operations are blocked by write and erase operations, leading to performance degradation.
Innovation Solution
A method and apparatus that set data read from busy flash chips to incorrect data, allowing reconstruction of correct data using data from other flash chips, thereby avoiding read operation blocking by write or erase operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If flash chips perform write and erase operations, then data storage and management functions are improved, but read operations are blocked causing increased read latency
Solution Approach 1:
The system divides the flash chip array into multiple independent chips, allowing read operations to proceed on chips not currently busy with write/erase operations. This segmentation enables concurrent operations across different chips, resolving the blocking issue while maintaining write/erase productivity.
Solution Approach 2:
The controller acts as an intermediary that manages read operations by directing requests to available flash chips. When a chip is busy, the controller waits for availability or redirects the read request to another chip, thereby mediating between write/erase operations and read operations to minimize latency.
2Reliability
If flash chips are in a busy state during write or erase operations, then data integrity during modification is maintained, but read operations cannot proceed
Solution Approach 1:
By segmenting the storage system into multiple independent flash chips, the system ensures that read operations can access chips that are not currently undergoing write/erase operations. This maintains data integrity during modifications while ensuring read operations remain available on other chips.
3Speed
If multiple flash chips are used in parallel, then read operation speed is improved, but system complexity increases
Solution Approach 1:
The controller is designed with multi-functionality to handle both read and write operations across multiple flash chips. It can detect chip status, direct read requests to available chips, and manage the complexity of parallel operations, thereby achieving high read speeds without proportionally increasing operational complexity.
Data Source
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AI summary
A method and an apparatus for reducing a read latency are disclosed. The method includes: when one or more flash chips corresponding to a read command are in a busy state, setting data read from the one or more flash chips in a busy state to wrong data; obtaining, according to the wrong data and data read from other flash chips, reconstructed correct data, and reporting the correct data. By using the present invention, data read from a flash chip is set to wrong data, and reconstructed correct data is obtained according to the wrong data and data read from other flash chips. In this way, when the flash chip is in a busy state, it can be avoided that a read operation is blocked by an erase operation or a write operation, thereby effectively reducing latency and improving a performance of a storage system.