Flash Memory Read Level Adjustment via Error Ratio Feedback

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Solution Overview

Problem

As flash memory ages or data retention times increase, the program level distributions of flash memory cells spread and shift, leading to increased read error rates, and existing read level adjustment algorithms are inefficient in determining when and how to adjust read levels.

Innovation Solution

A method for managing a data storage system that involves reading data from flash memory using a first read level voltage, determining bit-value errors, comparing error ratios to an error-ratio range, and adjusting the read level voltage based on these comparisons to minimize read errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If read level adjustment algorithms are implemented to reduce read error rates in aging flash memory, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improveread error rateVSAvoidalgorithm complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent adjusts read level voltages by changing electrical parameters in response to detected error patterns. The system modifies read level voltage values based on error ratios comparing first bit-value errors to second bit-value errors, thereby adapting to flash memory aging without complex algorithmic structures.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system implements feedback by monitoring error ratios during read operations and using this information to adjust subsequent read level voltages. The controller compares error ratios to reference ranges and iteratively refines read levels based on feedback from actual read performance, creating a closed-loop system that adapts to memory degradation.

Inventive Principle:
Principle #23Feedback

2Reliability

If frequent read level adjustments are made to maintain low error rates, then reliability is improved, but productivity decreases due to additional operations

Engineering Contradiction:
Improvebit error rateVSAvoidread operation efficiency
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The system performs read level adjustments periodically based on error ratio thresholds rather than continuously. Read operations proceed at normal speed, and adjustments are made only when error ratios indicate degradation, creating a periodic adjustment rhythm that maintains reliability without constantly interrupting productivity.

Inventive Principle:
Principle #19Periodic action

Solution Approach 2:

The patent applies adjustments only when and where needed based on error ratio comparisons. Rather than adjusting all read levels uniformly, the system selectively adjusts specific read levels based on detected error patterns, performing partial actions that maintain bit error rates without unnecessary operations that would reduce productivity.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If read level voltage is adjusted to compensate for flash memory aging, then reliability is improved, but measurement precision requirements increase

Engineering Contradiction:
Improvedata retentionVSAvoiderror ratio measurement
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The system establishes reference error ratio ranges in advance that define acceptable thresholds for read level performance. By pre-defining these measurement criteria, the system simplifies real-time measurements during operation, avoiding the need for complex real-time analysis while maintaining reliable detection of degradation patterns.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS20170263311A1Systems and methods for adaptive read level adjustment
Publication Date: 2017.09.14 WESTERN DIGITAL TECHNOLOGIES INC
  • US20170263311A1 patent drawing
  • US20170263311A1 patent drawing
  • US20170263311A1 patent drawing

AI summary

Reading requested data from flash memory using a first read level voltage. A number of first bit-value errors and a number of second bit-value errors is determined from the read requested data. An error ratio of the number of first bit-value errors and the number of second bit-value errors is compared to an error-ratio range. The first level voltage is adjusted based on the comparison of the error ratio to the error-ratio range.