Flash Memory Read Level Grouping for Error Reduction
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Solution Overview
Problem
Multi-level cell (MLC) flash memory devices experience significant degradation in program/erase cycles due to stress, leading to reduced endurance and increased errors in data retrieval, making them less reliable for enterprise applications compared to single-level cell (SLC) flash memory.
Innovation Solution
A method is implemented to read wordlines in flash memory devices multiple times using different read level voltages, generating error counts to create a table that indexes each error count by wordline and voltage, allowing for the selection of optimal read level voltages for future operations, thereby reducing errors and improving endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase data capacity, then storage capacity is improved, but reliability and endurance deteriorate due to increased wear from read, program and erase operations
Solution Approach 1:
The patent segments the flash memory into multiple blocks and implements wear-leveling algorithms that distribute write and erase operations across different blocks. This prevents any single block from experiencing excessive wear, thereby extending the overall endurance of MLC flash memory while maintaining high data capacity
Solution Approach 2:
The patent dynamically adjusts read level voltages based on measured error counts from sampling operations. By changing the read voltage parameters adaptively, the system compensates for voltage drift and degradation in MLC cells, improving reliability without sacrificing storage capacity
2Reliability
If multiple read level voltages are used to reduce bit error rates, then reliability is improved, but operation complexity and time increase
Solution Approach 1:
The patent performs preliminary sampling of error counts at different read levels during idle periods or configuration phases. These pre-measured error counts are stored and used to determine optimal read voltage levels, avoiding the need to perform complex multi-voltage reads for every data access operation
Solution Approach 2:
The system automatically measures error counts at different read levels and configures its own read voltage parameters without external intervention. The flash memory controller self-optimizes the read levels based on observed error patterns, reducing the operational burden on the system
3Measurement precision
If error counts are measured for each wordline and voltage combination, then read optimization is improved, but memory access time and processing overhead increase
Solution Approach 1:
Instead of measuring error counts for all wordlines and voltage combinations, the patent samples a representative subset of wordlines at different read levels. This partial measurement approach provides sufficient information to determine optimal read voltages without the time penalty of exhaustive measurement of every cell
Data Source
AI summary
A table of error counts is generated based on reading wordlines of a flash memory device, the table storing an error count for each combination of wordline and respective read level voltage used to read the wordlines. A plurality of offset wordline groups are generated based on the table of error counts, with each group associating a different read level offset voltage with a plurality of wordline addresses. A storage device is configured to read memory cells using a read level offset voltage of a generated offset wordline group associated with a wordline address of the memory cells to be read. After a predetermined point in a life cycle of a respective memory block, the table is regenerated and plurality of offset wordline groups are regenerated based the regenerated table of error counts.