Flash Memory Read Level Grouping for MLC Endurance
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Solution Overview
Problem
Multi-level cell (MLC) flash memory devices used in SSDs face reliability and endurance issues due to increased stress during read, program, and erase operations, leading to degradation, especially in enterprise applications where higher data capacity is needed but at a higher cost.
Innovation Solution
The method involves dividing flash memory wordlines into groups based on read error counts and normalized read level offsets, storing these associations to optimize read operations, thereby reducing bit error rates and improving endurance by using offset voltage pairs for consecutive wordlines in a flash memory block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If MLC flash memory is used to increase data capacity, then storage capacity is improved, but reliability and endurance deteriorate due to increased stress during read, program, and erase operations
Solution Approach 1:
The patent divides the flash memory array into multiple tiers or zones based on wear characteristics. Frequently accessed data is moved to a smaller SLC cache portion, while less frequently accessed data resides in the larger MLC portion. This segmentation allows the system to maintain high data capacity in MLC while protecting reliability by isolating high-stress operations to the more durable SLC portion.
Solution Approach 2:
The patent applies different quality characteristics to different portions of the storage system. The SLC cache portion is optimized for high endurance and fast operations, while the MLC portion is optimized for high capacity and cost-effectiveness. This local quality differentiation allows each portion to perform its specific function optimally without compromising the other.
2Reliability
If wear-leveling algorithms are employed to mitigate reliability problems, then reliability is improved, but device complexity increases
Solution Approach 1:
The wear-leveling algorithm is simplified by segmenting the storage space into distinct SLC and MLC portions with different wear characteristics. This allows the controller to apply different wear-leveling strategies to each portion, reducing the overall complexity compared to managing a uniform storage space. The SLC cache requires aggressive wear-leveling while the MLC portion can use more relaxed strategies.
Solution Approach 2:
The patent changes the parameters of the wear-leveling algorithm by introducing tier-specific parameters. Different wear thresholds, relocation frequencies, and allocation policies are applied to SLC and MLC portions. This parameter differentiation simplifies the algorithm by making it adaptive to the specific characteristics of each storage tier rather than requiring a single complex universal algorithm.
3Reliability
If read level offsets are normalized for best error rate, then bit error rate is reduced, but storage of offset associations increases memory requirements
Solution Approach 1:
The patent merges multiple offset associations into fewer representative offsets by grouping wordlines with similar read characteristics. Instead of storing individual offsets for each wordline, wordlines are clustered into groups with similar electrical characteristics, and a single offset is stored per group. This merging significantly reduces the memory required for offset storage while maintaining effective error rate reduction.
Solution Approach 2:
The patent changes the granularity parameter of offset storage from wordline-level to group-level. By adjusting this parameter, the system can trade off between precision (more offsets) and memory efficiency (fewer offsets). The optimal grouping size is determined based on the correlation of read characteristics across adjacent wordlines, achieving the best balance between error reduction and memory consumption.
Data Source
AI summary
A plurality of flash memory wordlines of a flash storage device are divided into a plurality of wordline groups based on read error counts associated with the wordlines and a plurality of read level offsets. Each wordline group is associated with one of a plurality of read level offsets determined while dividing the plurality of flash memory wordlines, and associations between the plurality of read level offsets and the plurality of wordline groups are stored for use in connection with read levels to read the flash memory wordlines of the respective wordline groups.