Flash Memory Read Parameter Adjustment for Fail Bit Reduction
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Solution Overview
Problem
The bit cost of SSDs is higher than HDDs, and the read processing performance of SSDs deteriorates significantly due to increased fail bits as flash memory blocks deteriorate with repeated erases, leading to difficulties in data recording and retention.
Innovation Solution
A semiconductor storage device with a controller that identifies storage area states and adjusts read parameters to optimize data retrieval from flash memory, reducing fail bits by using appropriate read parameters based on storage area conditions such as ambient temperature, elapsed time, and erase count.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory cells are downscaled to increase storage density, then storage capacity is improved, but the difference between injected and non-injected electron states is narrowed, increasing the probability of erroneous state determination and fail bits
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the read reference voltage based on the threshold voltage distribution characteristics of the flash memory cells. As cells deteriorate or as manufacturing variations occur, the optimal read reference voltage changes. The system monitors fail bit rates and modifies the read reference voltage parameter to maintain accurate state determination, thereby resolving the contradiction between high storage density and reliable data reading.
2Adaptability or versatility
If repeated erases are performed to enable data rewriting, then adaptability is improved, but cell deterioration increases and the number of possible erases is decreased
Solution Approach 1:
The patent implements feedback by continuously monitoring the fail bit rate during read operations and using this information to adjust the read reference voltage. As cells undergo repeated erases and deteriorate, the feedback mechanism detects increased fail bits and modifies the read parameters accordingly, allowing the system to maintain reliable operation throughout the cell's usable life and maximize the number of rewrite cycles.
Solution Approach 2:
The system transitions from using a fixed read reference voltage to a dynamic read reference voltage that adapts to cell deterioration. The read reference voltage is adjusted in real-time based on monitored performance characteristics, enabling the flash memory to maintain optimal reading conditions throughout repeated erase cycles and extend its operational lifespan.
3Speed
If inappropriate read parameters are used, then read processing speed is maintained, but a large number of fail bits occur, overwhelming correction codes and causing data loss
Solution Approach 1:
The patent resolves this contradiction by dynamically optimizing the read reference voltage parameter based on real-time monitoring of fail bit rates and cell state characteristics. The system adjusts the read reference voltage to match the current threshold voltage distribution, ensuring accurate state determination while maintaining efficient read processing speeds, thereby preventing data loss from overwhelming correction codes.
Data Source
AI summary
A semiconductor storage device has a nonvolatile semiconductor memory comprised from multiple storage areas, and a controller, which is coupled to the nonvolatile semiconductor memory. The controller (A) identifies a storage area state, which is the state of a storage area, (B) decides, based on the storage area state identified in the (A), a read parameter, which is a parameter for use when reading data from a storage area with respect to a storage area of this storage area state, and (C) uses the read parameter decided in the (B) with respect to a read-target storage area and reads data from this read-target storage area.