Flash Memory Read Architecture With Adaptive Threshold Estimation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional flash memory systems face performance degradation due to fixed default read thresholds, which are inadequate under varying stress conditions, leading to increased latency and read retry rates.
Innovation Solution
A configurable hardware architecture with row-to-row (R2R) estimation and machine learning-based read threshold adaptation, allowing real-time optimization of read operations without performance degradation, using a DNN engine for fast and accurate threshold estimation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If fixed default read thresholds are used, then device complexity is reduced, but read reliability deteriorates under varying stress conditions
Solution Approach 1:
The patent implements dynamic read threshold adjustment by transitioning from fixed thresholds to adaptive thresholds that change based on stress conditions. The system monitors stress indicators (temperature, voltage, operation count) and dynamically modifies read thresholds accordingly, allowing the memory device to maintain optimal read performance across varying operating conditions without requiring complex hardware redesign.
Solution Approach 2:
The patent changes the parameter of read thresholds from static fixed values to dynamic adaptive values. By modifying threshold parameters based on stress condition parameters (temperature, voltage, cycle count), the system achieves improved read reliability while maintaining manageable device complexity through parameter-based adaptation rather than structural complexity.
2Reliability
If adaptive read threshold methods are implemented, then read reliability improves, but read operation time increases
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing threshold adjustment values in lookup tables during manufacturing or idle periods. When a read operation occurs, the system queries pre-computed threshold values based on current stress conditions rather than performing complex real-time calculations, thereby improving reliability through adaptive thresholds while minimizing time overhead.
Solution Approach 2:
The patent uses copying by replicating threshold configuration data in multiple locations (lookup tables, registers, and potentially non-volatile memory). This allows the system to quickly retrieve and apply appropriate thresholds without performing time-consuming computations during critical read operations, balancing reliability improvement with time efficiency.
3Adaptability or versatility
If multiple processors generate configurations, then system versatility improves, but device complexity increases
Solution Approach 1:
The patent implements universality by designing a common configuration management framework that can be accessed and utilized by multiple processors. Instead of requiring separate dedicated hardware for each processor's configuration needs, the system provides a shared resource where any processor can generate and apply configurations, thereby improving versatility while avoiding the complexity multiplication that would result from dedicated hardware per processor.
Solution Approach 2:
The patent introduces an intermediary configuration management layer that mediates between multiple processors and the memory device. This intermediary layer handles the complexity of configuration generation, storage, and application, allowing multiple processors to access the system without directly increasing hardware complexity. The intermediary abstracts the complexity away while enabling versatile multi-processor operation.
Data Source
AI summary
In some embodiments, a flash memory system may include a non-volatile memory, a controller, a first processor, and a second processor. The first processor may generate a first configuration including a pointer to a first set of predefined configurations among a plurality of predefined configurations. In response to generating the first configuration, the circuit may generate, in a memory, the first set of predefined configurations. The controller may execute a first operation according to the first set of predefined configurations generated in the memory. The second processor may generate a second configuration comprising a pointer to a second set of predefined configurations among the plurality of predefined configurations. In response to generating the second configuration, the controller may generate, in the memory, the second set of predefined configurations. The controller may execute a second operation according to the second set of predefined configurations generated in the memory.