Flash Memory Read Voltage Adaptation for Charge Distribution Drift

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Solution Overview

Problem

Flash memory units experience disturbances in electric charge distribution due to factors like write/program, read, and retention disturbances, leading to incorrect data retrieval as threshold voltage distributions change over time, making it challenging to accurately read data without individually testing each gate voltage combination.

Innovation Solution

A memory controller with a control logic circuit, receiving circuit, data processing circuit, and storage unit that determines an electric charge distribution parameter and uses a look-up table to find a target gate voltage combination, allowing for quicker and more accurate data retrieval by adapting to changes in charge distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional reading methods with fixed gate voltage combinations are used, then the reading process is simple, but data reading accuracy deteriorates due to charge distribution changes from disturbances

Engineering Contradiction:
Improvedata reading accuracyVSAvoidreading process complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by pre-calculating and storing multiple gate voltage combinations in a look-up table before actual data reading operations. When reading data, the system first determines the appropriate gate voltage combination from the pre-prepared table based on disturbance conditions, then applies it to read the data. This eliminates the need for real-time complex calculations and ensures accurate reading even when charge distribution has changed due to disturbances.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the gate voltage parameter dynamically by selecting different gate voltage combinations from the look-up table based on the detected disturbance conditions and charge distribution state. Instead of using a fixed gate voltage combination, the system adapts the voltage parameters to match the current state of the flash memory, thereby maintaining reading accuracy despite changes in charge distribution over time.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If multiple gate voltage combinations are tested individually to find the correct one, then reading accuracy improves, but reading time increases significantly

Engineering Contradiction:
Improvereading accuracyVSAvoiddata reading time
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent pre-calculates and stores multiple gate voltage combinations in a look-up table during the design or initialization phase. During actual data reading, the system simply queries the pre-computed table to find the appropriate voltage combination based on current conditions, avoiding time-consuming individual testing of each combination. This preliminary preparation resolves the contradiction by making the selection process instantaneous rather than sequential.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent creates a copy of the threshold voltage distribution characteristics and stores it in the look-up table. Instead of performing actual reading operations with multiple different gate voltage combinations to test which one works, the system uses the pre-stored voltage combination data that replicates the optimal reading conditions, thereby achieving accurate reading without the time penalty of exhaustive testing.

Inventive Principle:
Principle #26Copying

3Ease of operation

If fixed threshold voltage settings are used for reading, then the control process is simple, but data retrieval becomes incorrect as P/E count and retention time change

Engineering Contradiction:
Improvecontrol process simplicityVSAvoiddata retrieval correctness
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent transforms the static, fixed threshold voltage setting into a dynamic system that adapts to changing conditions. The look-up table contains multiple gate voltage combinations that correspond to different states of the flash memory (different P/E counts and retention times). The system dynamically selects the appropriate voltage combination from the table based on the current state, maintaining both operational simplicity and retrieval correctness throughout the memory's lifecycle.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the control parameter (gate voltage combination) based on the detected state of the flash memory. Instead of using a single fixed threshold voltage setting, the system adjusts the voltage parameters by selecting from multiple pre-defined combinations in the look-up table, ensuring that the control parameters remain appropriate even as the memory undergoes programming/erasing cycles and retains data over time.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS12164377B2Method, memory controller, and memory system for reading data stored in flash memory
Publication Date: 2024.12.10 SILICON MOTION INC
  • US12164377B2 patent drawing
  • US12164377B2 patent drawing
  • US12164377B2 patent drawing

AI summary

An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.