3D Flash Memory Read Voltage Control for Background Pattern Dependency
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Solution Overview
Problem
The increasing number of stacked layers in three-dimensional flash memory leads to structural and electrical property challenges, including the background pattern dependency effect, which causes threshold voltage distribution broadening and reduces the read window margin, leading to read disturb and other issues.
Innovation Solution
The method involves adjusting the pass voltage applied to unselected memory cells during the read operation based on the program order of the selected memory cell, dividing memory cells into groups, and controlling the pass voltage differently for each group to mitigate the background pattern dependency effect and reduce read disturb.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stacked layers in three-dimensional flash memory is increased to increase bit density and reduce bit cost, then storage capacity is improved, but structural and electrical property challenges arise including threshold voltage distribution broadening and read window margin reduction
Solution Approach 1:
The patent applies different pass voltages to different groups of unselected memory cells based on their position and program order. Specifically, unselected memory cells are divided into multiple groups, with each group receiving a customized pass voltage level. This local differentiation addresses the threshold voltage distribution broadening by providing tailored voltage compensation to specific regions, thereby maintaining read window margin despite increased stacking layers.
Solution Approach 2:
The patent dynamically adjusts the pass voltage parameter applied to unselected memory cells during read operations. By changing the pass voltage level according to the program order and position of selected memory cells, the system compensates for background pattern dependency effects and threshold voltage shifts, thus preserving read reliability while maintaining high bit density through increased stacking layers.
2Ease of operation
If uniform pass voltage is applied to all unselected memory cells during read operation, then operation simplicity is maintained, but background pattern dependency effect causes threshold voltage distribution broadening and read disturb
Solution Approach 1:
Instead of applying a uniform pass voltage to all unselected memory cells, the patent divides them into multiple groups and applies different pass voltage levels to each group. This local quality approach targets the specific regions affected by background pattern dependency with customized voltage levels, reducing read disturb while maintaining manageable operational complexity through systematic voltage assignment.
Solution Approach 2:
The patent segments the population of unselected memory cells into multiple groups based on their position and program order characteristics. Each segment receives a differentiated pass voltage level, allowing the system to address background pattern dependency effects in a structured manner. This segmentation transforms a complex uniform voltage control problem into manageable discrete groups, balancing operational simplicity with read reliability.
Data Source
AI summary
Examples of the present disclosure provide a memory and an operation method thereof, a memory system and an electronic device. The operation method comprises: applying a pass voltage to word lines coupled to unselected memory cells of one of memory strings according to a program order of a selected memory cell of the memory string when performing a read operation on the selected memory cell, wherein the earlier the program order of the selected memory cell is, the greater the pass voltage applied to the word lines coupled to the unselected memory cells of the memory string during the read operation is. In the examples of the present disclosure, the pass voltage applied to the word lines coupled to the unselected memory cells is determined according to the program order of the selected memory cell, i.e., according to different degrees of impact of a background pattern dependency effect experienced by the selected memory cell, such that the impact of the background pattern dependency effect can be decreased, and the read disturb is reduced.