Flash Memory Read Voltage Tuning for Charge Distribution Drift
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Solution Overview
Problem
Flash memories face challenges in accurately reading data due to disturbances in electric charge distributions caused by program/erase cycles and data retention, leading to incorrect threshold voltage settings and unsuccessful codeword error corrections.
Innovation Solution
A memory controller with a control logic circuit, receiving circuit, and data processing circuit that selects an initial gate voltage combination, performs codeword error correction, and determines an electric charge distribution parameter to find a target gate voltage combination using a look-up table, allowing for quicker and more accurate control of flash memory units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If original gate voltage settings are used for reading flash memory, then reading operation can be performed, but data reading accuracy deteriorates due to charge distribution changes from program/erase cycles and retention time
Solution Approach 1:
The patent dynamically adjusts gate voltage parameters based on detected charge distribution characteristics. Instead of using fixed original gate voltage settings, the system modifies voltage levels adaptively to compensate for charge distribution changes caused by program/erase cycles and retention time, thereby maintaining accurate data reading despite memory degradation
Solution Approach 2:
The patent implements a feedback mechanism where the system detects actual charge distribution parameters from the flash memory and uses this information to adjust subsequent gate voltage settings. This closed-loop approach ensures that reading operations adapt to changing memory conditions, preventing reading errors that would occur with static voltage settings
2Measurement precision
If multiple gate voltage combinations are tested to find the correct one, then reading accuracy can be improved, but reading time increases significantly
Solution Approach 1:
The patent performs preliminary detection of charge distribution parameters before the actual data reading operation. By characterizing the memory state in advance and determining appropriate gate voltage settings beforehand, the system avoids time-consuming iterative testing during the critical data reading phase, thus maintaining both accuracy and speed
Solution Approach 2:
The patent transitions from static gate voltage selection to dynamic voltage adjustment based on real-time memory conditions. The system adaptively determines optimal voltage combinations based on detected charge distributions, eliminating the need for exhaustive testing of multiple fixed voltage options and enabling faster, condition-specific reading operations
3Reliability
If adaptive charge distribution tracking is implemented, then uncorrectable errors are reduced, but system complexity increases due to additional detection and processing circuits
Solution Approach 1:
The patent designs the memory controller to perform multiple functions using integrated circuits. The same control logic and processing units that manage normal read/write operations are extended to also perform charge distribution detection and adaptive voltage adjustment, eliminating the need for completely separate dedicated circuits and thereby limiting the increase in overall system complexity
Data Source
AI summary
An exemplary method for reading data stored in a flash memory includes: selecting an initial gate voltage combination from a plurality of predetermined gate voltage combination options; controlling a plurality of memory units in the flash memory according to the initial gate voltage combination, and reading a plurality of bit sequences; performing a codeword error correction upon the plurality of bit sequences, and determining if the codeword error correction successful; if the codeword error correction is not successful, determining an electric charge distribution parameter; determining a target gate voltage combination corresponding to the electric charge distribution parameter by using a look-up table; and controlling the plurality of memory units to read a plurality of updated bit sequences according to the target gate voltage combination.