Flash Memory Retention Extension via Re-energization
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Solution Overview
Problem
Flash memory bit cells in existing technologies lose charge over time, leading to data retention issues, with existing error correction codes only able to correct single bit errors before multiple errors occur, necessitating a method to improve long-term retention without altering clock cycle determinism.
Innovation Solution
A method that periodically re-energizes the Flash memory array by identifying and correcting single bit errors using a reFLASH process, which includes a reFLASH sub-system with a second data port, SRAM for shadowing user contents, and a real-time clock to manage power and error correction, allowing for single ROW or PAGE erase operations without invalidating content.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If Flash memory is used for storage, then non-volatile data retention is achieved, but charge loss over time causes data retention issues
Solution Approach 1:
The patent implements periodic re-energization of Flash memory blocks by monitoring retention counters and selectively re-programming blocks that have exceeded retention thresholds. This periodic maintenance action restores charge levels in affected blocks, extending overall data retention beyond the natural charge decay limits of Flash memory.
Solution Approach 2:
The system employs feedback mechanisms through retention counters that track the age of each Flash block and error detection circuits that monitor for charge loss. When errors are detected or thresholds are exceeded, the system automatically triggers re-programming operations to restore data integrity, creating a closed-loop control system for data retention.
2Reliability
If error correction code is used to correct single bit errors, then data integrity is maintained, but multiple errors cannot be corrected before data loss occurs
Solution Approach 1:
The patent performs preliminary re-programming actions before multiple bit errors can accumulate and cause data loss. By periodically re-energizing blocks based on retention counters and re-programming them proactively, the system prevents the accumulation of multiple errors that would exceed ECC correction capabilities.
Solution Approach 2:
The system introduces an intermediary re-programming operation between the original programming and potential multiple error occurrence. This intermediate maintenance action restores charge levels and prevents the transition from single correctable errors to multiple uncorrectable errors.
3Reliability
If Flash memory blocks are re-programmed frequently to maintain retention, then data retention is improved, but endurance cycles are consumed
Solution Approach 1:
The patent applies local quality by selectively re-programming only those Flash blocks that have exceeded retention thresholds or show signs of charge loss, rather than uniformly re-programming all blocks. This targeted approach maintains data retention for affected blocks while minimizing unnecessary endurance cycle consumption in already healthy blocks.
Solution Approach 2:
The system dynamically changes the operational parameters of Flash blocks by adjusting their retention counters and selectively applying re-programming based on monitored conditions. This parameter-based control allows the system to extend retention for blocks needing maintenance while preserving endurance cycles for blocks that still meet retention requirements.
Data Source
AI summary
This invention is a method to extend data retention for FLASH based storage in a real time device embodied in generic semiconductor technology. This invention provides a manner to re-energize the Flash memory array to improve the retention characteristics of the memory without altering the clock cycle determinism of the system. Under certain conditions the Flash memory bit cells will lose their charge/non-charge over time. In this particular FLASH technology, an ECC is used to correct single bit errors within a 32 bit word. If there is time before multiple errors occur within a word, the single error cases are identified and “ReFlashed” to bring the value of the cell back to its “newly” programmed levels. This dramatically improves the long term retention characteristics of the memory while requiring some control logic and an area of non-volatile scratch/status information.


