Flash Memory Array with Integrated ROM Cells and Shared Addressing
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Solution Overview
Problem
Historically, flash memory cells and ROM memory cells have differing architectures, sizes, and power requirements, making it inefficient to combine them in a single memory array with common addressing and sensing schemes, leading to large overhead and unreliability issues in flash memory arrays, especially in critical applications.
Innovation Solution
A memory array is designed with both flash and ROM memory cells sharing common addressing circuitry, read circuitry, and overhead circuitry, including a power source and voltage generator, allowing for efficient coexistence and addressing of both types of cells within a single array.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If flash memory cells and ROM memory cells are combined in a single memory array with common addressing circuitry, then space efficiency and cost are improved, but device complexity and reliability issues arise due to differing architectures and power requirements
Solution Approach 1:
The memory array is segmented into distinct flash memory cell regions and ROM memory cell regions, each with dedicated addressing and sensing schemes. This segmentation allows each cell type to be optimized for its specific characteristics while sharing common overhead circuitry, thereby reducing overall complexity compared to a unified approach.
Solution Approach 2:
Common addressing circuitry and overhead circuitry are designed to serve multiple functions by accommodating both flash memory cells and ROM memory cells. The addressing circuitry can selectively address different cell types based on the memory region being accessed, enabling a single circuit design to handle multiple memory technologies.
2Reliability
If flash memory cells and ROM memory cells use different architectures and sizes, then each cell type can be optimized for its specific function, but the memory array requires varying addressing and sensing schemes increasing overhead
Solution Approach 1:
Different addressing and sensing schemes are implemented for flash memory cell regions and ROM memory cell regions based on their specific architectural requirements. This local optimization ensures that each cell type is accessed using the most appropriate method, improving reliability while managing complexity through region-specific customization.
3Duration of action of stationary object
If flash memory cells are used in life-critical applications, then non-volatile storage is achieved, but data unreliability creates challenges
Solution Approach 1:
The patent combines flash memory cells and ROM memory cells in a single memory array, merging the benefits of non-volatile storage with the reliability of ROM. This combination allows the system to achieve both extended data retention and improved data integrity by leveraging the complementary strengths of both memory types.
Solution Approach 2:
ROM memory cells serve as an intermediary or backup mechanism within the memory array. When flash memory cells are accessed, the system can reference ROM memory cells to verify data integrity or provide fallback data, thereby mediating the reliability issues inherent in flash memory for life-critical applications.
Data Source
AI summary
Memory array for storing a plurality of data bits. The memory array has flash memory cells, ROM memory cells addressing circuitry. The addressing circuitry is operatively coupled to both the plurality of flash memory cells and the plurality of ROM memory cells, the addressing circuitry being configured to address both the plurality of flash memory cells and the plurality of ROM memory cells.