Flash Chip with Shared IO Pins for RPMC Integration
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Solution Overview
Problem
The integration of Flash and RPMC circuits into a single chip results in large size, high design complexity, and increased costs due to their combined design, leading to longer development times and higher costs.
Innovation Solution
An enhanced Flash chip design where Flash and RPMC are packaged independently with shared IO pins for external communication and internal communication through connected internal IO pins, allowing for parallel operation and reduced package size and design complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If Flash and RPMC are integrated into a single chip, then functionality is combined, but chip size and package size increase
Solution Approach 1:
The patent divides the enhanced Flash chip into two independent functional modules: Flash memory module and RPMC module. Each module has its own controller and can operate independently. This segmentation allows the modules to be designed separately and packaged together, reducing the overall package size compared to a fully integrated single-chip design while maintaining the combined functionality of both Flash and RPMC.
2Adaptability or versatility
If Flash and RPMC are designed together in a single chip, then integration is achieved, but design complexity increases
Solution Approach 1:
The patent segments the design process into independent modules: Flash controller design and RPMC controller design. Each controller is designed separately with its own logic and functionality. This modular design approach reduces design complexity by allowing independent optimization and verification of each module before integration, avoiding the need to design the entire system simultaneously.
Solution Approach 2:
The patent implements shared IO pins that can be used by both Flash and RPMC modules. The same physical pins serve multiple functions depending on which module needs to communicate at that moment. This multi-functionality reduces the total number of pins required, simplifying the interface design and reducing design complexity while maintaining full functionality of both modules.
3Adaptability or versatility
If Flash and RPMC are designed together in a single chip, then integration is achieved, but design period increases
Solution Approach 1:
The patent divides the development timeline into parallel tracks: Flash module development and RPMC module development can proceed simultaneously as separate projects. This segmentation enables concurrent engineering, significantly reducing the total design period compared to sequential integrated design, while still achieving integration in the final packaged product.
Solution Approach 2:
The patent allows individual modules (Flash and RPMC) to be designed, tested, and validated independently before final integration. This preliminary action on separate modules enables early verification of functionality and reduces debugging time during integration, thereby shortening the overall design period while achieving full integration.
4Adaptability or versatility
If Flash and RPMC are integrated into a single chip, then functionality is combined, but cost increases
Solution Approach 1:
The patent segments the manufacturing process into independent module fabrication and final packaging. Each module can be manufactured using optimized processes for that specific function, and then assembled together in a package. This approach reduces manufacturing cost by allowing specialization and avoiding the need for a completely new integrated chip fabrication process.
Solution Approach 2:
The patent uses shared IO pins and common packaging structures that serve both Flash and RPMC modules. This multi-functionality reduces the total component count and packaging complexity, lowering manufacturing costs while maintaining the combined functionality of both modules in the enhanced Flash chip.
Data Source
AI summary
An enhanced Flash chip and a method for packaging chip are provided to solve the problems of high design complexity. The enhanced Flash chip comprises: a FLASH and a RPMC packaged integrally, wherein the same IO pins in the FLASH and in the RPMC are mutually connected and are connected to the same external sharing pin of the chip; an external instruction is transmitted to the FLASH and the RPMC through the external sharing pin of the chip, and the controller of the FLASH and the controller of the RPMC respectively judge whether to execute the external instruction; and the FLASH and the RPMC further comprise internal IO pins, respectively, the internal IO pins of the FLASH and the internal IO pins of the RPMC are mutually connected, and internal mutual communication between the FLASH and the RPMC is performed through the pair of mutually connected internal IO pins.