Flash-SAR ADC Comparator Calibration for Accurate Fast Conversion
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Solution Overview
Problem
Flash ADCs face errors due to comparator offset and gain mismatch with SAR ADCs, leading to performance degradation, which can only be corrected by increasing redundancy bits or power consumption, compromising speed or area efficiency.
Innovation Solution
A calibration circuit tunes the reference voltage for each comparator in a flash ADC to reduce errors, implementing a hybrid flash-SAR ADC architecture that balances speed, area, and power consumption by calibrating the comparators before conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If redundancy bits are increased to correct comparator offset and gain mismatch errors, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing calibration of comparator reference voltages before the actual conversion operation. The calibration circuit pre-adjusts the reference voltages to compensate for offset and gain mismatch errors, so that when conversion occurs, the comparators are already optimized for accurate operation without requiring additional redundancy bits in the flash ADC structure
2Measurement precision
If power consumption is increased to improve error correction, then measurement precision is improved, but use of energy worsens
Solution Approach 1:
The calibration circuit performs reference voltage adjustment in advance before conversion, enabling accurate operation without requiring continuous high power consumption during conversion. The SAR ADC portion consumes less power during operation compared to a full flash ADC with redundancy bits, while the calibration phase uses moderate power to establish accurate reference voltages
Solution Approach 2:
The patent changes the reference voltage parameter dynamically through calibration. By adjusting the reference voltage levels to compensate for comparator errors, the system achieves high precision without increasing power consumption during the actual conversion operation, as the correction is embedded in the reference voltage settings rather than requiring additional active correction circuits
3Productivity
If flash ADC is used to achieve high conversion speed, then productivity is improved, but area of stationary object worsens
Solution Approach 1:
The patent segments the ADC into two parts: a flash ADC portion for high-speed conversion of the most significant bits, and a SAR ADC portion for converting the remaining bits with lower speed requirements. This segmentation allows the system to achieve high overall conversion speed without requiring a full flash ADC structure, thereby reducing the circuit area while maintaining productivity
Solution Approach 2:
The patent employs dynamic operation by using a calibration circuit that adjusts reference voltages based on detected errors. The system dynamically adapts the reference voltage levels to compensate for comparator variations, enabling the flash-SAR hybrid ADC to maintain high conversion speed with reduced area compared to a static full flash ADC design
Data Source
AI summary
Certain aspects provide a circuit for analog-to-digital conversion. The circuit generally includes a flash analog-to-digital converter (ADC) having a plurality of comparators, each comparator being configured to compare an input voltage to a reference voltage; and a calibration circuit coupled to the flash ADC and configured to tune the reference voltage prior to a conversion operation by the flash ADC.