FLASH-SAR ADC Timing Scheme for Parallel Coarse-Fine Quantization
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Solution Overview
Problem
Traditional FLASH-SAR ADCs suffer from low conversion efficiency due to the serial operation mechanism, which leads to wasted time during quantization stages and introduces aperture errors.
Innovation Solution
A new combined operating sequence for FLASH-SAR ADCs where the FLASH ADC performs amplification, comparison, and high-bit coarse quantization simultaneously with SAR ADC sampling, allowing fine quantization of residual voltage during the same cycle, optimizing the operating sequence to avoid independent clock cycles and reduce errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional SAR ADC serial operation mechanism is used, then structure is simple and power consumption is low, but conversion speed is severely limited
Solution Approach 1:
The ADC conversion process is segmented into two independent parallel paths: FLASH ADC for high-bit coarse quantization and SAR ADC for low-bit fine quantization. This segmentation allows simultaneous operation of both converters, achieving high-speed conversion while maintaining reasonable complexity by dividing the conversion task across different architectural approaches.
Solution Approach 2:
The patent merges FLASH ADC and SAR ADC into a hybrid architecture where both converters operate concurrently on the same input signal. The FLASH ADC handles high bits while the SAR ADC handles low bits, and their results are combined through digital logic to produce the final N-bit output, achieving speed improvement without proportionally increasing overall system complexity.
2Productivity
If FLASH ADC quantization is performed in a separate clock cycle after SAR ADC sampling, then quantization can be completed, but conversion efficiency is reduced due to wasted time
Solution Approach 1:
The FLASH ADC performs its amplification and comparison operations during the same sampling clock cycle when the SAR ADC is sampling, rather than waiting for a separate clock cycle. This preliminary action during the sampling phase eliminates idle time and ensures that both converters are productive simultaneously, improving conversion efficiency.
Solution Approach 2:
The patent ensures continuous useful action by making the FLASH ADC operational throughout the entire sampling period. Instead of having the FLASH ADC idle during sampling and then performing quantization in a separate phase, both converters operate continuously and concurrently, maximizing productivity and minimizing time loss.
3Measurement precision
If FLASH ADC and SAR ADC operate in separate phases, then each converter can function independently, but aperture errors are introduced due to time delays
Solution Approach 1:
The FLASH ADC completes its amplification and comparison operations during the sampling phase itself, before the sampling period ends. This preliminary completion of quantization operations ensures that the FLASH ADC result is ready simultaneously with the SAR ADC sampling, eliminating time delays that would otherwise cause aperture errors between the two conversion results.
Solution Approach 2:
By merging the timing operations of FLASH ADC and SAR ADC into a synchronized concurrent operation, the patent ensures that both converters process the same input signal at the same time. This temporal alignment through merging eliminates aperture errors that would arise from sequential processing, while maintaining independent functional operation of each converter.
Data Source
AI summary
A FLASH-SAR ADC conversion method comprises: at a sampling stage of a FLASH-SAR ADC, sampling an input signal by a SAR ADC module, and at the same time, performing amplification, comparison and high-bit coarse quantization on the input signal by a FLASH ADC module to output a FLASH ADC conversion result, wherein the FLASH ADC conversion result is a temperature code; at a conversion stage of the FLASH-SAR ADC, performing fine quantization on a residual voltage by the SAR ADC module according to the temperature code and the input signal to output a SAR ADC conversion result, and at the same time, sampling a reference voltage or a partial voltage of the reference voltage by FLASH ADC module; and performing encoding on the temperature code and the SAR ADC conversion result to obtain a signal conversion result of the FLASH-SAR ADC.