Flash Memory Scrambling Control for Low-Power Data Bus Switching
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Solution Overview
Problem
Conventional flash memory systems experience high power consumption due to frequent voltage level oscillations on the data bus when scrambling data, which shortens the operational time of portable devices and degrades their performance.
Innovation Solution
A flash memory device and controller that generate pseudo-random scrambled signals and calculate their transmission powers to select the signal with the lowest power requirement for storage, reducing power consumption by minimizing voltage level fluctuations on the data bus.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is scrambled using conventional pseudo-random sequences, then data distribution is improved (bits 0 and 1 are randomly distributed), but power consumption increases due to frequent voltage level oscillations on the data bus
Solution Approach 1:
The patent changes the parameters of the scrambling sequence by using multiple different pseudo-random sequences instead of a single conventional sequence. By selecting from multiple sequences with different characteristics, the system can find sequences that reduce voltage oscillations while maintaining good data distribution, thus resolving the contradiction between reliability and power consumption
Solution Approach 2:
The system dynamically selects different scrambling sequences based on the characteristics of the data being transmitted. Rather than using a fixed scrambling sequence, the controller adapts its choice of sequence to minimize voltage oscillations for each data set, thereby reducing power consumption while maintaining effective data scrambling
2Reliability
If conventional scrambling is used to prevent massed bits 0 or 1, then error bit rate is reduced, but voltage level oscillation increases causing high power consumption
Solution Approach 1:
The patent modifies the scrambling parameters by introducing multiple pseudo-random sequences with different properties. This allows the system to change the scrambling characteristics to achieve both low error bit rates and reduced voltage oscillations, simultaneously improving reliability and reducing energy loss
Solution Approach 2:
The patent segments the data transmission into multiple groups, each scrambled with a different pseudo-random sequence. This segmentation allows the system to optimize each segment's scrambling characteristics, achieving effective error prevention while minimizing overall power consumption through selective sequence usage
Data Source
AI summary
A method for controlling access operations of a flash memory includes: receiving first source data from a host; generating a plurality of first scrambled signals according to a plurality of pseudo random sequences and the first source data; obtaining a plurality of transmission powers of the first scrambled signals; and selecting a target scrambled signal from the first scrambled signals according to the transmission powers for storing to the flash memory. An associated flash memory device and an associated flash memory controller are also provided.