Flash Memory Select Gate Layout for Shorter Access Transistors
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Solution Overview
Problem
Traditional semiconductor manufacturing methods face limitations in shrinking the minimum gate length of access transistors due to feature mismatches and the need for thick photoresistors, which hinder the reduction of space between polysilicon layers in flash memory cells.
Innovation Solution
A manufacturing method that involves forming stacked gates with a floating gate and a control gate, using an etch-back process to create symmetric select gates without a mask, allowing for simultaneous formation of transistors and enabling easier shrinking of access transistors by depositing a select gate conductive layer and etching to form spacers on the sidewalls of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a mask is used when forming an access transistor to prevent cell leakage, then cell leakage is prevented, but feature differences between left and right cells occur, limiting the ability to shrink the minimum gate length
Solution Approach 1:
The patent removes the mask step from the access transistor formation process. Instead of using a mask to define the transistor regions, the method uses self-aligned etching where the transistor gates themselves serve as the alignment reference, eliminating mask-related feature differences while maintaining leakage prevention
Solution Approach 2:
The patent introduces intentional asymmetry in the etching process by using different etch conditions for left and right sides, allowing the minimum gate length to be reduced without being constrained by mask symmetry requirements, thus enabling further scaling while maintaining reliability
2Manufacturing precision
If a thick photo resistor is used for etching floating gate polysilicon, ONO layer, and control gate polysilicon, then etching precision is improved, but the space between polysilicon layers cannot be reduced
Solution Approach 1:
The patent transitions from using thick photoresist in the horizontal plane to using thin film deposition and vertical etching processes. The select gate conductive layer is deposited as a thin film that conforms to the stacked gate structure, and etching proceeds vertically to form spacers, enabling precise control of layer spacing without requiring thick photoresist
Solution Approach 2:
The patent changes the thickness parameter of the photoresist from thick to thin, and compensates for precision requirements by changing the etching process parameters and using the stacked gate structure as a self-aligned template, thereby reducing the space between polysilicon layers while maintaining etching precision
3Device complexity
If traditional manufacturing methods are used, then process simplicity is maintained, but the space between polysilicon layers of the floating gate cannot be reduced
Solution Approach 1:
The patent combines multiple formation steps into a single integrated process. The select gate conductive layer is deposited over the entire stacked gate structure in one step, and subsequent etching simultaneously forms spacers on both left and right sides, reducing the number of separate lithography and etching cycles needed while enabling smaller spacing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for the symmetric formation of select gates, facilitating the shrinking of access transistors and ensuring identical electrical performance, thus overcoming the limitations of traditional methods.
Implementation Method 1
forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate
Implementation Method 2
forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate
Data Source
AI summary
A manufacturing method of a semiconductor device, includes providing a substrate; forming a stacked gate, including a floating gate and a control gate, on the substrate; forming a stacked gate by a deposition of a select gate conductive layer on the stacked gate; forming a trench in the stacked gate by etching the stacked gate to separate a first select gate pattern and a second select gate pattern; and forming a first select gate, a second select gate, a first transistor, and a second transistor simultaneously through an etch-back process of the stacked gate.