Flash Memory Sense Amplifier Boost Circuit for Sensing Speed
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Solution Overview
Problem
Conventional sense amplifiers for flash memory face limitations in sensing speed, particularly when detecting a logical zero, due to the time required to charge and sense the bitline capacitance, which slows down the overall memory operation.
Innovation Solution
Incorporating a boost circuit with a pull-up section and a pull-down section, where the pull-up strength is twice that of the column load and the pull-down strength is twice that of the memory cell when storing a logical one, to enhance the sensing speed by reducing the impedance in the main cell current branch.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional sense amplifier circuits are used, then the circuit structure is simple, but the sensing speed is slow due to bitline capacitance charging time
Solution Approach 1:
The sense amplifier is divided into two independent branches: a reference cell current branch and a main cell current branch. Each branch operates independently with its own column load and drain bias circuit, allowing parallel processing and faster sensing by eliminating sequential operation delays
Solution Approach 2:
A differential amplifier is introduced as an intermediary component to compare the reference cell voltage with the main cell voltage. This intermediary device amplifies the voltage difference signal, enabling faster detection of stored data states without requiring direct measurement of small voltage changes
2Reliability
If the column load and drain bias circuits are added to maintain proper voltage levels, then the drain voltage is maintained at appropriate levels, but the sensing time increases
Solution Approach 1:
The drain bias circuits are configured to pre-establish appropriate drain voltage levels for both the reference cell and main cell before the sensing operation begins. This preliminary voltage setup eliminates the need for time-consuming voltage adjustments during the sensing process
Solution Approach 2:
The column loads are designed to dynamically convert cell currents to voltages with optimized time constants, and the drain bias circuits adjust voltage parameters to maintain optimal operating points, enabling faster voltage transitions while maintaining stability
3Speed
If the pull-up strength is increased to twice that of the column load and pull-down strength is increased to twice that of the memory cell, then the voltage crossing speed is improved, but the power consumption increases
Solution Approach 1:
The boost circuit is designed with dynamically controllable pull-up and pull-down transistors whose strengths are adjusted based on the sensing requirements. The pull-up strength is set to twice the column load and pull-down strength to twice the memory cell, providing optimized voltage crossing speed only when needed during the sensing window
Solution Approach 2:
The boost circuit operates periodically during the sensing operation, activating the enhanced pull-up and pull-down strengths only during the critical voltage crossing phase, then deactivating them to reduce power consumption during steady-state operation
Data Source
AI summary
A sense amplifier has a reference cell current branch in which a reference cell determines a reference cell current, a column load converts the reference cell current to a reference voltage, and a feedback circuit to maintain the reference cell drain voltage. The sense amplifier also has a main cell current branch in which a main cell operationally selected from an array of flash memory cells determines a main cell current, a column load converts the main cell current to a main voltage, and a feedback circuit to maintain the main cell drain voltage. A differential amplifier compares the reference voltage with the main voltage and furnishes a logical level at its output depending on the relative values. A boost circuit has a pull up section coupled across the column load and a pull down section coupled across the main cell for accelerating the logical zero sensing time.