Asymmetrical Flash Memory Sensing Amplifier Design
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Solution Overview
Problem
Current flash memory systems face challenges in achieving low power consumption while maintaining read accuracy, as existing sensing amplifiers do not efficiently utilize the full voltage range from ground to Vdd during read operations.
Innovation Solution
The proposed flash memory system incorporates improved sensing amplifiers that compare flash memory cells with dummy cells, utilizing a comparator and transistors to dynamically adjust reference voltages and bitline coupling signals, enabling a larger portion of the voltage range to be utilized during read operations, and includes features like cross-coupled inverter pairs and differential input pairs to generate built-in offsets and dynamically tune reference voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional sensing amplifiers are used, then the circuit structure is simple, but the voltage range utilization is limited and read accuracy deteriorates
Solution Approach 1:
The sensing amplifier is divided into multiple functional blocks: a first sensing amplifier for initial sensing, a second sensing amplifier for enhanced sensing, and associated control logic. This segmentation allows each block to perform specific functions that collectively improve voltage range utilization and read accuracy while managing complexity through modular design
Solution Approach 2:
The sensing amplifier employs dynamic voltage adjustment mechanisms where reference voltages and bitline coupling signals are dynamically tuned during read operations. The system adaptively switches between different sensing modes and adjusts voltage levels based on detected signal conditions, enabling full voltage range utilization from ground to Vdd
2Use of energy by moving object
If conventional sensing amplifiers are used, then the circuit design is straightforward, but power consumption cannot be optimized
Solution Approach 1:
The sensing amplifier operates in periodic cycles, alternating between active sensing phases and low-power standby phases. The control logic enables the amplifier to enter sleep modes when not actively sensing, and dynamically activates full-power operation only when needed, thereby optimizing power consumption through periodic operation patterns
Solution Approach 2:
The system dynamically changes operating parameters including voltage levels, current thresholds, and sensing amplification factors based on detected signal conditions. By adjusting these parameters adaptively, the sensing amplifier optimizes power consumption for each specific read operation while maintaining read accuracy
Data Source
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AI summary
Non-volatile memory device comprising: a first array of flash memory cells; a second array of dummy flash memory cells; a sensing amplifier coupled to a selected flash memory cell in the first array and a dummy flash memory cell in the second array during a read operation, the sensing amplifier comprising: a comparator for comparing a selected bit line coupled to the selected flash memory cell and a dummy bit line coupled to the dummy flash memory cell; a first circuit for applying a bias voltage to the selected bit line and a second circuit for applying a bias voltage to the dummy bit line; and a built-in sensing offset.