Flash Memory Sensing Circuit Low Voltage Operation
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Solution Overview
Problem
Existing sensing circuits for flash memory devices require high operating voltages (1.8-3.3 volts) and consume significant power, failing to function effectively at lower voltages and compensating for transistor mismatch and memory array non-idealities.
Innovation Solution
The development of lower power, lower voltage sensing circuits that utilize capacitors to decouple the differential amplifier from the memory data and reference read blocks, allowing for precharging and auto-zeroing to compensate for transistor mismatch and array mismatch, enabling operation at voltages as low as 1.1 volts and optimizing power supply levels.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If existing sensing circuits are used, then they can read data from memory cells, but they require high operating voltages (1.8-3.3 volts) and consume significant power
Solution Approach 1:
The sensing circuit performs preliminary actions by precharging the differential amplifier output nodes to a known state before the actual sensing operation. This precharging phase prepares the circuit for accurate comparison at lower voltages by establishing initial conditions that compensate for voltage-dependent variations in transistor characteristics
Solution Approach 2:
A capacitor is introduced as an intermediary element between the memory cell and the differential amplifier. This capacitor stores charge during the precharging phase and maintains voltage levels during sensing, acting as a buffer that decouples the amplifier from direct voltage variations in the memory cell, thereby enabling reliable operation at reduced voltages
2Measurement precision
If existing sensing circuits are used, then data reading is possible, but transistor mismatch and memory array non-idealities affect performance
Solution Approach 1:
The sensing circuit employs feedback mechanisms where the differential amplifier continuously monitors the voltage difference between the memory cell and reference cell, and adjusts its output accordingly. This feedback loop compensates for transistor mismatch by automatically balancing the signal paths, improving measurement precision without requiring complex external compensation circuitry
Solution Approach 2:
The circuit creates equipotential conditions by precharging both the memory cell node and reference node to the same initial voltage state before sensing. This ensures that both transistors operate under identical voltage conditions during the comparison phase, equalizing their effective characteristics and eliminating mismatch errors
3Productivity
If higher bit line currents are used, then sensing speed improves, but power consumption increases
Solution Approach 1:
The sensing operation is divided into distinct periodic phases: a precharging phase where bit line current is applied to establish initial conditions, and a sensing phase where current is reduced or redirected for voltage comparison. This periodic action allows the circuit to achieve fast sensing speeds during the active phase while minimizing power consumption during the transition and holding phases
Data Source
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AI summary
Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.