Flash Memory Sensing Circuit with Pre-Charge Control
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Solution Overview
Problem
The data read speed in flash memory is delayed due to excessive parasitic capacitance in the sensing circuit, which loads the circuit and slows down data access.
Innovation Solution
A sensing circuit for flash memory that includes a first transistor, a detector, and a charge circuit, where the detector enables a control signal when the voltage of the transistor's drain is below a threshold, allowing the charge circuit to charge the source until the voltage reaches the threshold, thereby enhancing data read performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a large amount of memory cells are coupled to the sensing circuit, then the memory capacity is increased, but the parasitic capacitance increases causing excessive load and delayed data read speed
Solution Approach 1:
The charge circuit performs preliminary charging of the sensing node before the actual read operation. By pre-charging the node to a predetermined voltage level, the circuit reduces the time required for voltage stabilization during the read operation, thereby improving data read speed while maintaining the ability to handle large numbers of memory cells.
Solution Approach 2:
The sensing operation is divided into distinct periodic phases: a pre-charge phase where the charge circuit charges the sensing node, and a read phase where the actual data reading occurs. This periodic structure allows the circuit to reset and prepare before each read operation, maintaining high speed performance across multiple reads.
2Quantity of substance
If the sensing circuit handles more memory cells, then the memory density is increased, but the load on the sensing circuit increases causing performance degradation
Solution Approach 1:
The charge circuit performs preliminary charging of the sensing node before the actual read operation. By pre-charging the node to a predetermined voltage level, the circuit reduces the time required for voltage stabilization during the read operation, thereby improving data read speed while maintaining the ability to handle large numbers of memory cells.
Solution Approach 2:
The circuit dynamically controls the charging voltage and timing parameters of the charge circuit based on the read operation requirements. By adjusting these parameters, the circuit can optimize performance for different memory cell configurations and maintain high productivity even as memory density increases.
Data Source
AI summary
A sensing circuit for a flash memory is provided. The sensing circuit includes a first transistor, a detector, and a charge circuit. A drain of the first transistor is coupled to a bias, a gate thereof receives an inverted signal, and a source thereof receives a data. In addition, the drain of the first transistor is further coupled to the detector. Therefore, the detector detects a voltage of the drain of the first transistor. When the voltage of the drain is lower than a threshold voltage, the detector enables a control signal. The charge circuit charges the source of the first transistor when the control signal is enabled, until the voltage of the drain of the first transistor reaches the threshold voltage.