Flash Memory Cell With Shallow Trench Channel For Area Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The limitation of channel length in NOR flash memory cells restricts the size reduction of memory cells, leading to issues like read current leakage and poor hot electron programming distribution, particularly for nodes less than 45 nm, where the channel length is more than 100 nm, limiting the minimum memory cell area to 10F2.
Innovation Solution
The introduction of a first shallow trench in the channel region of the memory cell, with a tunneling dielectric layer on its surface and a polysilicon floating gate that fully fills the trench, allowing for a longitudinal channel structure that increases channel length while reducing the polysilicon floating gate length, thereby minimizing the memory cell area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the channel length is increased to satisfy short channel effect (more than 100 nm), then the reliability is improved, but the memory cell area increases to at least 10F2
Solution Approach 1:
The patent introduces a first shallow trench in the channel region, transforming the channel structure from a planar two-dimensional layout to a three-dimensional structure with vertical depth. The tunneling dielectric layer is formed on the bottom surface and side surfaces of the trench, creating a纵向 channel that extends along the trench depth, thereby increasing channel length without proportionally increasing the planar footprint of the memory cell
Solution Approach 2:
The tunneling dielectric layer is nested within the first shallow trench structure, with the polysilicon floating gate fully filling the trench. This nested configuration allows the channel-forming dielectric layer to occupy the vertical space within the trench, effectively utilizing the third dimension to achieve longer channel length while maintaining compact planar dimensions
2Productivity
If the polysilicon floating gate length is decreased to reduce memory cell area, then the productivity is improved, but the channel length becomes insufficient causing short channel effect
Solution Approach 1:
By forming the first shallow trench with depth in the vertical direction, the patent decouples the relationship between planar gate length and channel length. The tunneling dielectric layer extends along the trench depth, creating a longitudinal channel structure where channel length is determined by trench depth rather than gate length, enabling short gates with long channels
3Ease of manufacture
If planar technology is used for nodes more than 45 nm, then the ease of manufacture is maintained, but the minimum memory cell area is limited to 10F2
Solution Approach 1:
The patent segments the channel region by introducing a first shallow trench that divides the channel into distinct regions: the trench region with vertical channel structure and the surrounding planar regions. This segmentation allows the trench-based vertical channel to coexist with planar device structures, enabling enhanced density in specific areas while maintaining overall planar technology compatibility for manufacturing
Data Source
AI summary
The present invention discloses a flash. A channel region comprises a first shallow trench formed in the surface area of a semiconductor substrate. A tunneling dielectric layer and a polysilicon floating gate are formed in the first shallow trench and extended to the outside of the first shallow trench. A control dielectric layer and a polysilicon control gate are sequentially formed on the two side surfaces in the width direction and the top surface of the polysilicon floating gate. A source region and a drain region are formed in a self-aligned manner in active regions on the two sides in the length direction of the polysilicon floating gate. The present invention further discloses a method for manufacturing a flash. The present invention can break through the limitation of the length of the channel on the size of the memory cell, thus reducing the area of the memory cell.