Flash Memory Soft-Bit Compression for ECC Bandwidth Limits
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Solution Overview
Problem
Existing memory devices face inefficiencies in error correction due to resource-intensive soft bit generation and transmission, which complicates data storage and retrieval processes, especially with conventional lossless and lossy compression algorithms.
Innovation Solution
The implementation of fixed size soft bit lossy compression, which reduces complexity and data loss while achieving a good compression ratio by compressing soft bits into smaller fixed sizes, allowing for efficient data processing and distribution across memory spaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If soft bits are generated and transferred to improve error correction capability, then error correction reliability is improved, but system bandwidth is reduced and resources are consumed
Solution Approach 1:
The patent extracts only the essential reliability information from soft bits by identifying and retaining only the most significant bits that contribute to error correction, while discarding less critical bits. This selective extraction maintains error correction capability while reducing the total number of bits transferred over the bus.
Solution Approach 2:
The patent applies different quality levels to different portions of soft bit data by prioritizing certain bits over others based on their importance for error correction. Not all soft bits are treated equally - only those with highest significance are retained and transferred, creating a non-uniform quality distribution that optimizes the reliability-bandwidth tradeoff.
2Reliability
If additional sensing operations are performed to generate soft bits, then error correction capability is improved, but resource consumption increases
Solution Approach 1:
The patent extracts only the necessary reliability information from soft bits through selective bit retention, avoiding the need to process, store, and transfer complete soft bit sets. This extraction approach reduces computational and memory resources required while maintaining sufficient error correction capability.
3Loss of information
If conventional lossless compression algorithms are used, then data integrity is maintained, but implementation complexity increases due to variable length requirements
Solution Approach 1:
The patent enforces uniform fixed-length encoding for all compressed soft bit data, eliminating the variable length characteristics of conventional lossless compression algorithms like Huffman coding. This homogenization of data structure simplifies hardware implementation by allowing consistent buffer sizes, fixed addressing schemes, and simplified control logic.
Solution Approach 2:
The patent accepts some information loss in exchange for dramatically reduced implementation complexity, using simple fixed-size compression that can be implemented with basic logic circuits rather than complex variable-length decoding trees. This approach prioritizes practical implementability over perfect data recovery.
4Reliability
If soft bits are transferred over the bus, then error correction is improved, but bandwidth availability for other operations is reduced
Solution Approach 1:
The patent extracts and transfers only the most critical soft bit information rather than complete soft bit sets, significantly reducing the number of bits occupying bus bandwidth. This selective transmission maintains essential error correction capability while freeing bandwidth for other memory operations.
Solution Approach 2:
The patent transfers a partial set of soft bit information - enough to provide meaningful error correction capability but not the full information set. This partial action approach achieves sufficient reliability improvement without the excessive bandwidth consumption of complete soft bit transfer.
Data Source
AI summary
A memory includes, in one embodiment, one or more storage elements; read/write circuitry; and compressed bit circuitry. The read/write circuitry is configured to read a set of hard bits from the one or more storage elements, and sense a set of soft bits while reading the set of hard bits from the one or more storage elements, the set of soft bits having a first fixed size, and the set of soft bits indicating a reliability of the set of hard bits. The compressed soft bit circuitry is configured to generate, with a fixed size soft bit lossy compression algorithm, a fixed size compressed soft bits by compressing the set of soft bits, the fixed size compressed soft bits having a second fixed size that is smaller than the first fixed size, and output the fixed size compressed soft bits to a memory-to-controller bus.