Embedded Flash Source Line Recess for Accurate Parallel Sensing
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Solution Overview
Problem
Conventional embedded flash memory devices suffer from source line bias error due to substantial current through the source line, leading to voltage drops and accuracy issues in sensing operations, particularly in memory architectures where multiple memory cells share a common source line.
Innovation Solution
A semiconductor memory device design featuring a substrate with a pair of floating gates, a recessed source line doped region with a concave profile between 40 nm and 60 nm radius, an erase gate, a word line adjacent to the floating gates, and a bit line doped region, which reduces source line resistance and improves sensing accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a large number of memory cells share a common source line, then parallel sensing capability is improved, but source line resistance causes voltage drop and sensing accuracy deteriorates
Solution Approach 1:
The source line doped region is segmented into multiple regions corresponding to different memory blocks, with each region independently connected to its respective memory cells. This segmentation reduces the effective resistance in each segment while maintaining parallel sensing capability across multiple blocks simultaneously.
Solution Approach 2:
The source line doped region is formed with a concave profile having a radius between 40 nm and 60 nm, creating locally optimized electrical characteristics. This local structural modification reduces resistance in critical areas without affecting the overall architecture's parallel sensing capability.
2Measurement precision
If source line doped region has conventional flat profile, then manufacturing is simpler, but resistance is higher and sensing accuracy is lower
Solution Approach 1:
The source line doped region is formed with a concave profile instead of a flat surface, with a specified radius between 40 nm and 60 nm. This curved geometry reduces resistance by increasing the effective doped area and improving charge distribution, while the specific radius range optimizes the balance between performance improvement and manufacturing feasibility.
Data Source
AI summary
A semiconductor memory device includes a substrate, a pair of floating gates disposed on the substrate, a source line doped region in the substrate between the floating gates, an erase gate disposed between the floating gates and on the source line doped region, a word line disposed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate, and a bit line doped region in the substrate and adjacent to the word line. An upper surface of the source line doped region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates.