Embedded Flash Source Line Recess Layout for Accurate Sensing

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Solution Overview

Problem

Conventional embedded flash memory devices suffer from source line bias error due to substantial current through the source line, leading to voltage drops and accuracy issues in sensing operations, particularly in memory architectures where multiple memory cells share a common source line.

Innovation Solution

A semiconductor memory device is designed with a recessed region between floating gates, featuring a source line doped region with a concave profile and specific dimensions, an erase gate, and word lines, which reduces source line resistance and improves sensing accuracy.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a large number of memory cells share a common source line, then device complexity is reduced and integration is improved, but source line resistance increases causing voltage drops and sensing accuracy degradation

Engineering Contradiction:

Improvememory cell architecture complexityVSAvoidsensing operation accuracy

Core Design Contradiction:

Device complexityVSMeasurement precision

Solution Approach 1:

The source line is segmented into multiple separate source lines, with each source line serving a subset of memory cells. This segmentation reduces the total resistance of each source line segment, thereby reducing voltage drops during sensing operations while maintaining the integrated memory array architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Different source lines are assigned to different regions or groups of memory cells, creating local quality variations in the source line resistance characteristics. This allows each local group to have optimized source line resistance suitable for accurate sensing, while the overall device maintains integration benefits.

Inventive Principle:

Principle #3Local quality

2Loss of energy

If source line resistance is reduced by increasing source line cross-sectional area, then voltage drops are mitigated, but device area increases

Engineering Contradiction:

Improvevoltage drop in source lineVSAvoiddevice area

Core Design Contradiction:

Loss of energyVSArea of stationary object

Solution Approach 1:

Instead of increasing the cross-sectional area of a single source line, the current path is segmented into multiple parallel source lines. Each source line maintains a reasonable cross-sectional area, but the parallel configuration reduces total resistance and voltage drops without requiring a single oversized conductor.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The solution transitions from increasing dimension (cross-sectional area) in one source line to distributing current across multiple source lines in the horizontal dimension, effectively using spatial distribution to reduce resistance without concentrating area in a single location.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS20240332383A1Semiconductor memory device and fabrication method thereof

Publication Date: 2024.10.03 UNITED MICROELECTRONICS CORP

AI summary

A method for forming a semiconductor memory device is disclosed. A substrate is provided. A pair of floating gates are formed on the substrate. A recessed region is formed in the substrate between the floating gates, wherein an upper surface of the recessed region has a concave profile lower than a surface of the substrate and with a radius between 40 nm and 60 nm in a cross-sectional view perpendicular to the floating gates. A source line doped region is formed in the recessed region. An erase gate is formed between the floating gates and on the recessed region, and a word line is formed on the substrate and adjacent to a side of each of the floating gates opposite to the erase gate. A bit line doped region is formed in the substrate and adjacent to the word line.