Flash Memory Endurance Extension via SRAM Caching Controller
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Solution Overview
Problem
Flash memories used in single-chip products have limited endurance and data retention due to their high frequency of access operations, which reduces their lifetime compared to EEPROMs.
Innovation Solution
A memory apparatus combining a flash memory unit with a static random access memory (SRAM) unit and a controller that manages data access by comparing write data with SRAM data, executing writes only when necessary, and rearranging data when the flash memory page is full, thereby reducing the number of access operations and extending the flash memory's endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If flash memory is used to replace EEPROM in single-chip products, then the memory capacity and integration are improved, but the endurance and data retention are significantly reduced
Solution Approach 1:
The memory system is divided into two distinct memory units: a first memory unit (flash memory) for large-capacity data storage and a second memory unit (EEPROM or similar) for storing critical data that requires high endurance. This segmentation allows each memory type to be used in its optimal application, resolving the contradiction between capacity and reliability.
Solution Approach 2:
A controller acts as an intermediary between the host and the two memory units, intelligently managing data placement, access, and wear distribution. The controller directs write operations to appropriate memory units based on data characteristics, monitors wear levels, and performs data migration when needed, thereby extending the overall system endurance while maintaining high capacity.
2Speed
If flash memory access operations are performed frequently, then the data access speed is improved, but the lifetime of the flash memory is reduced
Solution Approach 1:
The system dynamically adjusts the access pattern between the two memory units based on real-time conditions such as wear level, access frequency, and data criticality. The controller can migrate data between memory units, change access policies, and balance wear distribution dynamically, allowing the system to maintain high access speeds while extending the operational lifetime of the flash memory.
Solution Approach 2:
The controller periodically monitors the wear status of the flash memory and performs data migration or access pattern adjustments at scheduled intervals or when thresholds are reached. This periodic maintenance approach prevents excessive wear accumulation while maintaining optimal performance, resolving the contradiction between frequent access and lifetime extension.
3Productivity
If data is written frequently to flash memory, then the data update capability is improved, but the number of erase cycles increases reducing reliability
Solution Approach 1:
The system performs preliminary actions by pre-allocation of memory spaces, pre-computation of wear distribution, and proactive data migration before the flash memory reaches its erase cycle limit. The controller anticipates wear accumulation and redistributes data in advance, allowing frequent data updates without proportionally increasing the risk of exceeding erase cycle limits.
Solution Approach 2:
The system discards data from heavily worn flash memory blocks and recovers their capacity by migrating data to less worn blocks or the second memory unit. This wear leveling and recovery approach enables continuous data updates while managing the finite erase cycle resource, maintaining productivity without sacrificing reliability.
Data Source
AI summary
A memory apparatus and a data access method thereof are provided. The memory apparatus includes a first memory unit and a second memory unit, wherein an access speed of the second memory unit is higher than an access speed of the first memory unit. The method includes: receiving write data and a corresponding write address; comparing the write data with data corresponding to the write address in the second memory unit, so as to determine whether to write the write data into a current physical memory page of the first memory unit and into the second memory unit; after a data writing operation is executed, executing a data arranging operation on the current physical memory page according to the data in the second memory unit when the current physical memory page is full; and when a read command is received, reading the corresponding data in the second memory unit.