3D Flash Memory Stack With Erasing Layer to Protect Tunnel Dielectric
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Solution Overview
Problem
The performance of three-dimensional (3D) flash semiconductors deteriorates over time due to the reduced effectiveness of the tunnel dielectric layer during repeated data storage and erasure processes, leading to decreased functionality.
Innovation Solution
The semiconductor design incorporates a stack structure with a specific arrangement of control gate layers, dielectric layers, erasing layers, a floating gate layer, a blocking layer, a tunnel dielectric layer, and a channel layer, where the erasing layer is insulated from the control gate and floating gate, allowing electrons to move along a different path during erasure, thereby reducing the stress on the tunnel dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If electrons move between floating gate and channel layer through tunnel dielectric layer during repeated storing and erasing operations, then data storage and erasure functions are achieved, but the performance of tunnel dielectric layer is reduced and effective function is decreased
Solution Approach 1:
The patent segments the electron transport path by introducing an erasing layer that provides an alternative erasure path separate from the tunnel dielectric layer. During erasing operations, electrons can travel through the erasing layer instead of degrading the tunnel dielectric layer, while maintaining fast data storage capability through the original tunneling path.
Solution Approach 2:
The erasing layer acts as an intermediary structure that mediates the erasure operation. It provides a dedicated path for electron transport during erasing, protecting the tunnel dielectric layer from repeated stress while enabling continued high-speed data storage and erasure operations.
2Adaptability or versatility
If the tunnel dielectric layer is used for repeated electron transport during storing and erasing, then data manipulation functionality is maintained, but the layer dissipates and effectiveness is reduced
Solution Approach 1:
The patent divides the electron transport function into two separate paths: one for storing operations through the tunnel dielectric layer, and another for erasing operations through the erasing layer. This segmentation allows the tunnel dielectric layer to be used selectively for storing, extending its operational lifespan while maintaining full data manipulation versatility.
Solution Approach 2:
The patent changes the operational parameters by introducing voltage control mechanisms that direct electrons through different layers based on the operation type. During storing, high voltage enables tunneling through the dielectric layer; during erasing, voltage distribution shifts to utilize the erasing layer, thereby preserving the tunnel dielectric layer.
3Ease of manufacture
If a simple stack structure is used for flash memory, then manufacturing is easier, but repeated operations cause tunnel dielectric layer degradation
Solution Approach 1:
The patent extends the simple stack structure by adding the erasing layer as an additional segment. This maintains the vertical stacking manufacturing advantage while functionally segmenting the electron transport paths to prevent tunnel dielectric layer degradation during repeated operations.
Solution Approach 2:
The patent merges multiple functions into the extended stack structure: the tunnel dielectric layer handles fast storing operations, the erasing layer handles erasure operations, and both work together within a single integrated vertical stack, achieving both ease of manufacture and extended reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design extends the lifespan of the semiconductor by minimizing the dissipation of the tunnel dielectric layer, maintaining performance even with repeated data writing and erasing operations.
Implementation Method 1
electrons move between the floating gate and a channel layer by passing through a tunnel dielectric layer
Implementation Method 2
the erasing layer is insulated from the control gate and floating gate, allowing electrons to move along a different path during erasure
Data Source
AI summary
A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.