Flash Storage Interface Data Error Reduction

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Flash memory devices experience frequent data errors due to advancements in data transmission rates, necessitating methods to reduce errors in flash storage interfaces.

Innovation Solution

A processing unit continuously monitors data and control frames for errors and adjusts the transmission data rate when errors are detected, using the UFS interface's lowest layer to trigger adjustments between the host and device sides, operating at different speed gears.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data transmission rate is increased to improve productivity, then data transfer speed is improved, but data errors occur more frequently worsening reliability

Engineering Contradiction:
Improvedata transfer speedVSAvoiddata error rate
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent implements dynamic data rate adjustment where the transmission rate is not fixed but can change based on detected error conditions. The system transitions from a static high-speed mode to a dynamic rate-control mechanism that adapts to maintain reliability while maximizing throughput.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent employs feedback mechanisms where the receiving end monitors data integrity and sends feedback signals to the transmitting end. Based on this feedback about error detection, the system adjusts the transmission rate to resolve the contradiction between speed and reliability.

Inventive Principle:
Principle #23Feedback

2Reliability

If data rate adjustment mechanism is added to reduce errors, then reliability is improved, but device complexity increases

Engineering Contradiction:
Improvedata error reductionVSAvoidinterface control complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent makes the existing lowest layer of the flash storage interface multi-functional by enabling it to perform both data transmission and error monitoring and rate adjustment control. This eliminates the need for separate dedicated control hardware, thereby reducing overall device complexity while maintaining reliability improvements.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The system implements self-service error control where the lowest layer automatically monitors its own transmission quality and triggers rate adjustments without requiring external intervention. This autonomous operation reduces the complexity of external control mechanisms.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS10848263B2Methods for reducing data errors in transceiving of a flash storage interface and apparatuses using the same
Publication Date: 2020.11.24 SILICON MOTION INC
  • US10848263B2 patent drawing
  • US10848263B2 patent drawing
  • US10848263B2 patent drawing

AI summary

The invention introduces a method for reducing data errors in transceiving of a flash storage interface, performed by a processing unit of a first side, comprising: continuously monitoring data frames and/or control frames from a second side; and triggering a TX (transmission) data rate adjustment when information of the data frame and/or the control frame indicates that the lowest layer of the second side detects errors from received data.