Flash Storage Interrupt Control for Controller Workload Reduction
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Solution Overview
Problem
The burden on the storage device controller is increased due to cache memory management, and the energy provided by capacitors as standby power limits the size of the buffer memory in solid state storage devices, affecting performance.
Innovation Solution
A method and system for controlling interrupts during data transmission between a host and a storage device, where the storage device receives write requests, writes data to flash memory, and sends messages to the host indicating completion, with mechanisms to suppress interrupts if the message frequency exceeds a predetermined threshold, thereby offloading controller burden and optimizing buffer memory usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If cache memory is used to improve read/write speed, then reading and writing speed is improved, but controller complexity and management burden increase
Solution Approach 1:
The patent extracts the cache memory management function from the storage device controller and relocates it to the host system. The storage device only needs to provide basic DMA transmission capabilities, while the host's CPU and memory management unit handle cache allocation, maintenance, and optimization. This extraction significantly reduces controller complexity while preserving the performance benefits of cache memory.
2Reliability
If interrupt frequency is increased to improve data transmission responsiveness, then transmission reliability is improved, but controller workload increases
Solution Approach 1:
The patent implements periodic interrupt suppression mechanisms where the storage device sends interrupts to the host at controlled intervals rather than continuously. The host receives periodic notifications about data transmission status and cache memory conditions, which maintains adequate responsiveness while significantly reducing the frequency of interrupt handling operations and associated controller workload.
3Productivity
If buffer memory size is increased to improve data transmission efficiency, then transmission efficiency is improved, but energy consumption increases
Solution Approach 1:
The patent implements dynamic buffer memory management where the buffer size is adjusted based on real-time transmission conditions, data patterns, and energy availability. The system can expand buffer usage during high-priority transmissions and reduce it during low-activity periods, optimizing the balance between transmission efficiency and energy consumption rather than maintaining a fixed large buffer.
Data Source
AI summary
A method of controlling interrupts in the process of data transmission used for transmitting data between an information processing device and a storage device having a flash memory includes: receiving a write request sent by the information processing device using the storage device; in response to the write request, writing data to the flash memory; sending a message to the information processing device, to indicate completion of the write request, and calculating the number of times of sending messages to the information processing device within the predetermined time interval; in which, if the number is larger than the predetermined threshold, stopping the sending messages to the information processing device.