Multi-processor Flash Storage with Dedicated RAM and Bus Segmentation
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Solution Overview
Problem
Current Flash-based storage systems face performance bottlenecks due to single processor management over a shared bus, leading to slower data management speeds and limited scalability for robust systems, as well as RAM and bus contentions that hinder high-performance operations.
Innovation Solution
A distributed architecture for Flash storage devices with multiple microprocessor units, each having dedicated RAM and bus connections to Flash configurations, managed by a dataflow controller to optimize access and reduce contention, allowing for independent operation and improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single processor manages Flash storage over a shared bus, then device complexity is reduced, but data management speed and scalability deteriorate
Solution Approach 1:
The patent divides the single processor into multiple microprocessor units (MPUs), each capable of independently managing Flash storage operations. This segmentation allows parallel processing of data management tasks, thereby increasing data management speed while distributing the complexity across multiple simpler units rather than one complex processor.
Solution Approach 2:
The patent transitions from a single-dimensional processing model (one processor) to a multi-dimensional parallel processing architecture. Multiple MPUs operate simultaneously on different data blocks, utilizing temporal and spatial parallelism to enhance throughput without proportionally increasing bus complexity.
2Device complexity
If a shared bus is used for processor access to Flash memory, then device complexity is reduced, but bus contention and performance degradation occur
Solution Approach 1:
The shared bus architecture is segmented into multiple dedicated buses, with each MPU having its own private bus connection to Flash memory. This eliminates bus contention by providing multiple independent data pathways, ensuring consistent performance even under high utilization conditions.
Solution Approach 2:
The patent introduces a bus arbitration mechanism that acts as an intermediary to manage access requests from multiple MPUs to the Flash memory. This mediator coordinates bus usage to prevent conflicts and maintain reliable performance across the system.
3Device complexity
If RAM is shared among multiple processors, then device complexity is reduced, but RAM contention and data management speed deteriorate
Solution Approach 1:
The shared RAM is divided into dedicated memory regions assigned to each MPU. Each microprocessor unit has its own private RAM space for storing data blocks and management information, eliminating contention while maintaining overall system coherence through coordinated access protocols.
4Quantity of substance
If Flash memory is written frequently, then data storage capacity is improved, but mean time before failure deteriorates
Solution Approach 1:
The Flash memory is divided into multiple data blocks that can be independently managed. When one block becomes full or worn, the system can switch to another block, distributing write operations across multiple segments. This extends the overall lifespan of the Flash memory while maintaining full storage capacity.
Solution Approach 2:
The patent implements a wear-leveling strategy where Flash blocks are discarded (marked as full or worn) and later recovered (erased and reused) in a rotated fashion. This allows the system to continuously utilize full storage capacity while distributing wear evenly across all blocks, thereby extending mean time before failure.
Data Source
AI summary
A data storage device has a host controller interface, a plurality of microprocessor units each having a portion of random access memory (RAM) dedicated thereto, a plurality of Flash device configurations each having dedicated bus connections to individual ones or multiples of the microprocessor units, and a dataflow controller accessible to the host controller interface for managing access to the Flash device configurations.