Flash Storage Management Using Multiple Open Page Stripes
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional SSDs have a limited number of open page stripes that can be power-loss protected due to the small size of the write buffer, leading to inefficiencies and bottlenecks in storage systems, as they can only support a small number of partially filled page stripes.
Innovation Solution
The system implements a 'vertical/horizontal hybrid' method of writing data, where each page in a page stripe is filled sequentially before moving to the next die, reducing the power-loss protection requirement to only two pages per open page stripe, allowing for increased flexibility and protection of multiple open page stripes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the write buffer size is increased to support more open page stripes, then the number of power-loss protected page stripes increases, but the power consumption and cost of capacitors increases
Solution Approach 1:
The patent segments the write buffer into multiple independent cache lines, each capable of holding a portion of a page stripe. This allows the system to manage multiple open page stripes with a smaller total buffer capacity, reducing the power consumption of capacitors while maintaining support for more concurrent page stripes.
Solution Approach 2:
The patent changes the organizational parameters of the write buffer from traditional page-based to cache line-based structure, with each cache line holding a specific number of bytes (e.g., 256 bytes). This parameter change enables more efficient utilization of buffer space and reduces the total capacity needed to support multiple open page stripes.
2Quantity of substance
If the write buffer size is increased to support more open page stripes, then the number of power-loss protected page stripes increases, but the cost of the SSD increases
Solution Approach 1:
By segmenting the write buffer into smaller cache lines, the patent reduces the total buffer capacity required to support multiple open page stripes. This directly reduces the cost of capacitors and other power-loss protection components, making the SSD more cost-effective to manufacture.
Solution Approach 2:
The patent uses multiple cache lines that can be reused across different page stripes. Instead of dedicating large buffer space to each page stripe, the system creates virtual copies of buffer capacity through the cache line structure, reducing the physical hardware needed and thus the manufacturing cost.
3Use of energy by moving object
If the write buffer is made small to reduce power consumption and cost, then the number of open page stripes supported decreases, but the flexibility of host software is reduced
Solution Approach 1:
The patent implements a dynamic cache line allocation system where cache lines are allocated and deallocated based on the current state of page stripes. This dynamic management allows the system to support a high number of open page stripes with a small buffer by efficiently reusing cache lines as page stripes are closed and flushed, thereby maintaining software flexibility without increasing power consumption.
Solution Approach 2:
Each cache line in the write buffer is designed to be universal and can serve multiple page stripes throughout their lifecycle. A single cache line can hold data for one page stripe at a time, then be reused for another page stripe after the first is flushed. This multi-functionality allows a small buffer to support many concurrent page stripes, maintaining host software flexibility while keeping power consumption low.
4Use of energy by moving object
If the write buffer is made small to reduce power consumption and cost, then the number of open page stripes supported decreases, but the performance of the server is bottlenecked
Solution Approach 1:
The dynamic cache line management system continuously adapts to the workload by allocating cache lines to active page stripes and freeing them when page stripes are closed. This dynamic behavior ensures that the limited buffer capacity is always optimally utilized, preventing performance bottlenecks even with a small write buffer, while maintaining low power consumption.
Solution Approach 2:
The patent ensures continuous useful action by immediately recycling cache lines from closed page stripes for use in open page stripes. This continuous reuse of buffer space eliminates idle time in the write path, maintaining high server performance despite the small physical buffer size, while avoiding the need for larger (more power-consuming) buffers.
Data Source
AI summary
One embodiment facilitates flash storage management. During operation, the system receives a request to write data to a non-volatile memory. The system writes, in a buffer in association with a controller, the data to a next available portion of a current physical page in a page stripe, wherein the page stripe includes physical pages which each correspond to a sequentially ordered die of the non-volatile memory. The system provides power-loss protection to the current physical page and a second physical page which indicates parity information for the page stripe, thereby providing power-loss protection to an increased number of partially full page stripes.